XR17D158 Exar Corporation, XR17D158 Datasheet - Page 17

• Manufacturer Part Number: XR17D158
• Description: Eight-channel Pci-bus Uart
• Manufacturer: Exar Corporation

XR17D158
UNIVERSAL (3.3V AND 5V) PCI BUS OCTAL UART
REV. P1.0.0
The XR17D158 has a 32-bit wide register [INT0, INT1, INT2 and INT3] to provide interrupt information and
supports two interrupt schemes. The first scheme is an 8-bitan 8-bit indicator representing all 8 channels with
each bit representing each channel from 0 to 7. This permits the interrupt routine to quickly vector and serve
that UART channel and determine the source(s) in each individual routines. INT0 bit-0 represents the interrupt
status for UART channel 0 when its transmitter, receiver, line status, or modem port status requires service.
Other bits in the INT0 register provide indication for the other channels with bit-7 representing UART channel 7
respectively.
The second scheme provides detail about the source of the interrupts for each UART channel. All the interrupts
are encoded into a 3-bit code. This 3-bit code represents 7 interrupts corresponding to individual UART’s
transmitter, receiver, line status, modem port status. INT1, INT2 and INT3 registers provide the 24-bit interrupt
status for all 8 channels. Bits 8, 9 and 10 representing channel 0 and bits 29, 30 and 31 representing channel 7
respectively. All 8 channel interrupts status are available with a single DWORD read operation. This feature
allows the host quickly vectors and serves the interrupts, reducing service interval, hence, reduce host
bandwidth requirement.
All bits start up zero. A special interrupt condition is generated by the D158 upon awakening from sleep after all
8 channels were put to sleep mode earlier.
INT0 [7:0] Channel Interrupt Indicator
Each bit gives an indication of the channel that has requested for service. Bit-0 represents channel 0 and bit-7
indicates channel 7. Logic one indicates the channel N [7:0] has called for service. The interrupt bit clears after
reading the appropriate register of the interrupting channel register, see Interrupt Clearing section.
INT3, INT2 and INT1 [32:8] Twenty four bit encoded interrupt indicator. Each channel’s interrupt is encoded
into 3 bits for receive, transmit, and status. Bit [10:8] represent channel 0 and go up to channel 7 with bits
[31:29]. The 3 bit encoding and their priority order are shown below in
are for the device and therefore they exist within channel 0 space and not in other channel interrupt.
2.2.1
The Interrupt Status Register
GLOBAL INTERRUPT REGISTER (DWORD)
INT3 [31:24]
The INT0 register provides individual status for each channel
B it-7 B it-6 B it-5 B it-4 B it-3 B it-2 B it-1 B it-0
C h-7
Ind ivid ua l U A R T C h an ne l Interrup t S tatus
C h-6
INT2 [23:16]
Figure 6
C h-5 C h-4 C h-3 C h-2 C h-1 C h-0
IN T0 R egister
shows the 4-byte interrupt register and its make up.
17
INT1 [15:87]
[default 0x00-00-00-00]
Table
5. The Timer and MPIO interrupts
INT0 [7:0]
PRELIMINARY
áç
áç
áç
áç