WM8580AGEFT Wolfson Microelectronics Ltd., WM8580AGEFT Datasheet - Page 45

• Manufacturer Part Number: WM8580AGEFT
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
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Table 35 S/PDIF Transmitter Clock Control
PRIMARY AUDIO INTERFACE RECEIVER (PAIF RX)
The PAIF Receiver requires a left-right-clock (LRCLK) and a bit-clock (BCLK). These can be supplied
externally (slave mode) or they can be generated internally by the WM8580 (master mode). The
master mode LRCLK/BCLK are created by the Master Mode Clock Gen module. The control of this
module is described on page 22. The clock supplied to this module is selected by the
PAIFRXMS_CLKSEL register bits and can be MCLK, PLLACLK, or PLLBCLK.
Table 36 PAIF Receiver Master Mode Clock Control
Figure 29 PAIF Receiver Clock Selection
REGISTER
REGISTER
ADDRESS
ADDRESS
CLKSEL
PAIF 1
08h
09h
R8
R9
BIT
BIT
5:4
7:6
TX_CLKSEL
PAIFRXMS_
CLKSEL
LABEL
LABEL
DEFAULT
DEFAULT
01
00
S/PDIF Transmitter clock source
PAIF Receiver Master Mode clock
source
00 = ADCMCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
00 = MCLK pin
01 = PLLACLK
10 = PLLBCLK
11 = MCLK pin
DESCRIPTION
DESCRIPTION
PD Rev 4.3 August 2007
WM8580
45