WM8580AGEFT Wolfson Microelectronics Ltd., WM8580AGEFT Datasheet - Page 73

• Manufacturer Part Number: WM8580AGEFT
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
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Table 71 DR3 / DR4 Operation
The Secondary Audio Interface (SAIF) is not operational in Hardware Mode.
STATUS PINS
In Hardware control mode, SDO, SWMODE and MFP8/9/10 pins provide S/PDIF status flag
information.
Table 72 Hardware Mode Status Pins
DIGITAL AUDIO INTERFACE CONTROL
In Hardware Control Mode, CSB and SCLK become controls to configure the Primary Audio Interface
data format and word length. The configuration applies to both transmit and receive sides of the
interface. Table 73 below shows the options available.
Table 73 Audio Interface Hardware Mode Control
DAC MUTE CONTROL
In Hardware Control mode, the MUTE pin activates the softmute function on all the DACs. In
Software Control mode, MUTE activates softmute on the DAC selected by the DZFM register (when
the MPDENB bit is low). See section headed “MUTE MODES” for a detailed description of the
softmute function and the other methods of activating softmute.
When floating, the MUTE pin becomes an output for the ZFLAG flag.
SWMODE
MFP10
MFP8
MFP9
SDO
PIN
DR4
0
0
1
1
CSB
NON_AUDIO
0
0
1
1
SFRM_CLK
UNLOCK
192BLK
FLAG
C
Indicates that the S/PDIF Clock Recovery circuit is unlocked
or that the input S/PDIF signal is not present.
0 = Locked to incoming S/PDIF stream.
1 = Not locked to the incoming S/PDIF stream, or incoming
stream not present.
Logical OR of PCM_N and AUDIO_N:
PCM_N indicates that non-audio code (defined in IEC-61937)
has been detected. AUDIO_N is the recovered Channel
Status bit-1.
Recovered channel-bit for current sub-frame
Indicates current sub-frame:
1 = Sub-frame A
0 = Sub-frame B
Indicates start of 192-frame block. High for duration of frame
0, low after frame 0.
DR3
0
1
0
1
SCLK
0
1
0
1
DESCRIPTION
S/PDIF TRANSMITTER
ADC digital output data
S/PDIF received data
24-bit right justified
20-bit right justified
24-bit left justified
24-bit I
PAIF receiver data
FORMAT & WORD LENGTH
DATA SOURCE
2
PD Rev 4.3 August 2007
N/A
S
WM8580
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