WM8580AGEFT Wolfson Microelectronics Ltd., WM8580AGEFT Datasheet - Page 76

• Manufacturer Part Number: WM8580AGEFT
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

WM8580
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REGISTER
ADDRESS
REGISTER
DEVREV
PLLA 1/
DEVID1
PLLA 2/
DEVID2
PLLA 3/
PLLA 4
R39
R40
R41
R42
R43
R44
R45
R46
R47
R48
R49
R50
R51
R52
R53
00h
01h
02h
03h
R0
R1
R2
R3
NAME
SPDRXCHAN 1
SPDRXCHAN 2
SPDRXCHAN 3
SPDRXCHAN 4
SPDRXCHAN 5
READBACK
SPDSTAT
PWRDN 1
PWRDN 2
INTSTAT
RESET
GPO2
GPO3
GPO4
GPO5
BIT
8:0
8:0
3:0
7:4
4:3
0
1
FREQMODE_A[
POSTSCALE_A
PLLA_K[21:18]
PRESCALE_A
PLLA_K[17:9]
PLLA_N[3:0]
PLLA_K[8:0]
ADDRESS
LABEL
1:0]
2A
2B
2C
2D
2E
27
28
29
2F
30
31
32
33
34
35
ALWAYSVALID
B8
0
0
0
0
0
0
100100001
101111110
DEFAULT
B7
1101
0111
10
0
0
0
0
0
ALLDACPD
B6
GPO10OP[3:0]
GPO4OP[3:0]
GPO6OP[3:0]
GPO8OP[3:0]
0
0
Fractional (K) part of PLLA frequency ratio (R).
Value K is one 22-digit binary number spread over registers R0,
R1 and R2 as shown.
Reading from these registers will return the device ID.
Device ID readback is not possible in continuous readback mode
(CONTREAD=1).
Integer (N) part of PLLA frequency ratio (R).
Use values in the range 5 ≤ PLLA_N ≤ 13 as close as possible to
8.
Reading from this register will return the device revision number.
PLL Pre-scale Divider Select
0 = Divide by 1 (PLL input clock = oscillator clock)
1 = Divide by 2 (PLL input clock = oscillator clock ÷ 2)
Note: PRESCALE_A must be set to the same value as
PRESCALE_B in PLL S/PDIF receiver mode.
PLL Post-scale Divider Select
PLL S/PDIF Receiver Mode
POSTSCALE_A is used to configure a 256fs or 128fs PLLACLK,
POSTSCALE_B is not used. Refer to Table 45.
PLL User Mode
Used in conjunction with the FREQMODE_x bits. Refer to Table
44.
PLL Output Divider Select
PLL S/PDIF Receiver Mode
FREQMODE_A is automatically controlled. FREQMODE_B is not
used.
PLL User Mode
Used in conjunction with the POSTSCALE_x bits. Refer to Table
44.
Error Flag Interupt Status Register
B5
SPDIFRXD
Channel Status Register 1
Channel Status Register 2
Channel Status Register 3
Channel Status Register 4
Channel Status Register 5
S/PDIF Status Register
1
0
R0 returns 10000000 = 80h
R1 returns 10000101 = 85h
RESET
SPDIFTXD
B4
READEN
DACPD[2:0]
B3
SPDIFPD
CONTREAD
DESCRIPTION
B2
PLLBPD
GPO5OP[3:0]
GPO9OP[3:0]
GPO30P[3:0]
GPO70P[3:0]
B1
READMUX[2:0]
PLLAPD
ADCPD
PD Rev 4.3 August 2007
B0
OSCPD
PWDN
Production Data
DEFAULT
000110010
001010100
001110110
010011000
001111110
000111110
000000000
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
n/a
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