WM8580AGEFT Wolfson Microelectronics Ltd., WM8580AGEFT Datasheet - Page 53

• Manufacturer Part Number: WM8580AGEFT
• Description: Multichannel Codec with S/pdif Transceiver
• Manufacturer: Wolfson Microelectronics Ltd.

Production Data
Table 46 User Mode PLL Configuration Examples
w
(MHz)
OSC
CLK
12
12
12
12
12
12
12
24
24
24
24
24
24
24
27
27
27
27
SCALE
PRE-
_x
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
(MHz)
13.5
13.5
13.5
13.5
12
12
12
12
12
12
12
12
12
12
12
12
12
12
F
When considering settings not shown in this table, the key configuration parameters which must be
selected for optimum operation are:
CLOCK OUTPUT (CLKOUT) AND MCLK OUTPUT (MCLK)
The clock output (CLKOUT) pin can be used as a clock output. This pin is intended to be used as a
clock source pin for providing the central clock reference for an audio system.
The CLKOUT clock source can be selected from OSCCLK, PLLACLK or PLLBCLK. The
control bits for the CLKOUT signal are shown in Table 47.
The MCLK pin can be configured as an input or output – the WM8580 should be powered
down when switching MCLK between an input and an output. As an output, MCLK can be
sourced from OSCCLK, PLLACLK or PLLBCLK.
Table 47 MCLK and CLKOUT Control
1
REGISTER
ADDRESS
PLLB 4
•
•
•
07h
R7
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
90.3168
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
98.304
(MHz)
90MHz ≤ f
5 ≤ PLLx_N ≤ 13
OSCCLOCK = 10 to 14.4MHz or 16.28 to 27MHz
F
2
BIT
6:5
8:7
7.5264
7.5264
7.5264
7.5264
7.5264
7.5264
7.5264
7.2818
7.2818
6.6901
6.6901
8.192
8.192
8.192
8.192
8.192
8.192
8.192
2
R
≤ 100MHz
MCLKOUTSRC
CLKOUTSRC
PLLx_N
LABEL
(Hex)
8
8
8
8
8
8
8
7
7
7
7
7
7
7
7
7
6
6
2C2B24
PLLx_K
21B089
21B089
21B089
21B089
21B089
21B089
21B089
1208A5
1208A5
2C2B24
C49BA
C49BA
C49BA
C49BA
C49BA
C49BA
C49BA
(Hex)
DEFAULT
00
11
MODE_x
FREQ
[1:0]
00
01
01
10
10
11
11
00
01
01
10
10
11
11
00
01
00
01
MCLK pin output source
CLKOUT pin source
00 = Input – Source MCLK pin
01 = Output – Source PLLACLK
10 = Output – Source PLLBCLK
11 = Output – Source OSCCLK
00 = No Output (tristate)
01 = Output – Source PLLACLK
10 = Output – Source PLLBCLK
11 = Output – Source OSCCLK
SCALE_x
POST-
1
0
1
0
1
0
1
1
0
1
0
1
0
1
1
1
1
1
DESCRIPTION
PD Rev 4.3 August 2007
PLLxCLK
22.5792
22.5792
11.2896
11.2896
22.5792
11.2896
24.576
24.576
12.288
12.288
5.6448
7.5264
3.7632
24.576
12.288
(MHz)
6.144
8.192
4.096
WM8580
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