AT94K05AL ATMEL Corporation, AT94K05AL Datasheet - Page 134

• Manufacturer Part Number: AT94K05AL
• Description: Fpslic Devices Combine 5K Gates of Atmel's Patented AT40K Fpga Architecture, a 20 Mips Avr 8-bit Risc Microprocessor Core, Numerous Fixed Microcontroller Peripheries And up to 36K Bytes of Program And Data SRAM.
• Manufacturer: ATMEL Corporation

134
AT94K Series FPSLIC
The 2-wire Serial Data Register – TWDR
• Bits 7..0 - TWD: 2-wire Serial Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the 2-wire Serial Bus.
In transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR
contains the last byte received. It is writable while the 2-wire Serial Interface is not in the pro-
cess of shifting a byte. This occurs when the 2-wire Serial Interrupt flag (TWINT) is set by the
hardware. Note that the data register cannot be initialized by the user before the first interrupt
occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out,
data on the bus is simultaneously shifted in. TWDR always contains the last byte present on
the bus, except after a wake up from Power-down Mode, or Power-save Mode by the 2-wire
Serial Interrupt. For example, in the case of the lost bus arbitration, no data is lost in the tran-
sition from Master-to-Slave. Receiving the ACK flag is controlled by the 2-wire Serial Logic
automatically, the CPU cannot access the ACK bit directly.
The 2-wire Serial (Slave) Address Register – TWAR
• Bits 7..1 - TWA: 2-wire Serial Slave Address Register
These seven bits constitute the Slave address of the 2-wire Serial Bus interface unit.
• Bit 0 - TWGCE: 2-wire Serial General Call Recognition Enable Bit
This bit enables, if set, the recognition of the General Call given over the 2-wire Serial Bus.
The TWAR should be loaded with the 7-bit Slave address (in the seven most significant bits of
TWAR) to which the 2-wire Serial Interface will respond when programmed as a Slave trans-
mitter or receiver, and not needed in the Master modes. The LSB of TWAR is used to enable
recognition of the general call address ($00). There is an associated address comparator that
looks for the Slave address (or general call address if enabled) in the received serial address.
If a match is found, an interrupt request is generated.
Bit
$1F ($3F)
Read/Write
Initial Value
Bit
$1E ($3E)
Read/Write
Initial Value
7
MSB
R/W
1
7
MSB
R/W
1
6
R/W
1
6
R/W
1
5
R/W
1
5
R/W
1
4
R/W
1
4
R/W
1
3
R/W
1
3
R/W
1
2
R/W
1
2
R/W
1
1
R/W
1
1
LSB
R/W
1
Rev. 1138F–FPSLI–06/02
0
LSB
R/W
1
0
TWGCE
R/W
0
TWDR
TWAR