AT94K ATMEL Corporation, AT94K Datasheet - Page 103
AT94K
Manufacturer Part Number
AT94K
Description
5K - 40K Gates of At40k FPGA with 8-bit Microcontroller, up to 36K Bytes of SRAM and On-chip JTAG ICE
Manufacturer
ATMEL Corporation
Datasheet
1.AT94K.pdf
(192 pages)
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Rev. 1138F–FPSLI–06/02
Figure 56. Effects on Unsynchronized OCR1 Latching
Note:
Figure 57. Effects of Unsynchronized OCR1 Latching in Overflow Mode
Note:
During the time between the write and the latch operation, a read from OCR1A or OCR1B will
read the contents of the temporary location. This means that the most recently written value
always will read out of OCR1A/B.
When the OCR1X contains $0000 or TOP, and the up/down PWM mode is selected, the out-
put OC1A/OC1B is updated to Low or High on the next compare match according to the
settings of COM1A1/COM1A0 or COM1B1/COM1B0. This is shown in Table 31. In overflow
PWM mode, the output OC1A/OC1B is held Low or High only when the Output Compare Reg-
ister contains TOP.
Compare Value Changes
1. X = A or B
1. X = A or B
Unsynchronized
Synchronized
Unsynchronized OC1x
Compare Value Changes
Synchronized OC1x
OCR1X
OCR1X
(1)
(1)
(1)
Latch
Latch
(1)
Latch
Latch
Compare Value Changes
Compare Value Changes
AT94K Series FPSLIC
Glitch
PWM Output OC1x
PWM Output OC1x
Compare Value
Counter Value
PWM OutputOC1X
Counter Value
Compare Value
PWM OutputOC1X
(1)
(1)
(1)
(1)
103