LPC47M112 SMSC Corporation, LPC47M112 Datasheet - Page 36

• Manufacturer Part Number: LPC47M112
• Description: ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with LPC Interface
Datasheet
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps are
selected.
BITS 1 - 2 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data
rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.
BITS 3 - 6 UNDEFINED
Always read as a logic "1"
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
Model 30 Mode
BITS 0 - 1 DATA RATE SELECT
These bits control the data rate of the floppy controller. See Table 8 for the settings corresponding to the individual data
rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a hardware reset.
BIT 2 NOPREC
This bit reflects the value of NOPREC bit set in the CCR register.
BIT 3 DMAEN
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
BITS 4 - 6 UNDEFINED
Always read as a logic "0"
BIT 7 DSKCHG
This bit monitors the pin of the same name and reflects the opposite value seen on the disk cable or the value
programmed in the Force Disk Change Register (see Runtime Register at offset 0x1E).
CONFIGURATION CONTROL REGISTER (CCR)
Address 3F7 WRITE ONLY
PC/AT and PS/2 Modes
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 8 for the appropriate values.
BIT 2 - 7 RESERVED
Should be set to a logical "0"
SMSC DS – LPC47M112
RESET
COND.
RESET
COND.
CHG
DSK
N/A
N/A
7
7
N/A
6
0
0
6
DATASHEET
N/A
0
5
0
5
Page 36
N/A
4
0
0
4
DMAEN NOPREC DRATE
N/A
3
0
3
N/A
2
0
2
DRATE
SEL1
SEL1
1
1
1
1
DRATE
DRATE
SEL0
SEL0
0
0
0
0
Rev. 02/02/2005