LPC47M112 SMSC Corporation, LPC47M112 Datasheet - Page 63

• Manufacturer Part Number: LPC47M112
• Description: ENHANCED SUPER I/O CONTROLLER WITH LPC INTERFACE
• Manufacturer: SMSC Corporation

Enhanced Super I/O Controller with LPC Interface
Datasheet
1) "Software" resets (via the DOR or DSR registers) will only clear GAP and WGATE bits to "0". D0-D3 are unaffected
2) "Hardware" resets will clear all bits
LOCK
In order to protect systems with long DMA latencies against older application software that can disable the FIFO the
LOCK Command has been added. This command should only be used by the FDC routines, and application software
should refrain from using it. If an application calls for the FIFO to be disabled then the CONFIGURE command should
be used.
The LOCK command defines whether the EFIFO, FIFOTHR, and PRETRK parameters of the CONFIGURE command
can be RESET by the DOR and DSR registers. When the LOCK bit is set to logic "1" all subsequent "software RESETS
by the DOR and DSR registers will not change the previously set parameters to their default values. All "hardware"
RESET from the nPCI_RESET pin will set the LOCK bit to logic "0" and return the EFIFO, FIFOTHR, and PRETRK to
their default values. A status byte is returned immediately after issuing a LOCK command. This byte reflects the value
of the LOCK bit set by the command byte.
ENHANCED DUMPREG
The DUMPREG command is designed to support system run-time diagnostics and application software development
and debug. To accommodate the LOCK command and the enhanced PERPENDICULAR MODE command the eighth
byte of the DUMPREG command has been modified to contain the additional data from these two commands.
COMPATIBILITY
The LPC47M112 was designed with software compatibility in mind. It is a fully backwards- compatible solution with the
older generation 765A/B disk controllers. The FDC also implements on-board registers for compatibility with the PS/2, as
well as PC/AT and PC/XT, floppy disk controller subsystems. After a hardware reset of the FDC, all registers, functions
and enhancements default to a PC/AT, PS/2 or PS/2 Model 30 compatible operating mode, depending on how the
IDENT and MFM bits are configured by the system BIOS.
SMSC DS – LPC47M112
and retain their previous value.
(GAP, WGATE and D0-D3) to "0", i.e all conventional mode.
WGATE
0
0
1
1
GAP
Table 27 - Effects of WGATE and GAP Bits
0
1
0
1
Conventional
Perpendicular
(500 Kbps)
Reserved
(Conventional)
Perpendicular
(1 Mbps)
DATASHEET
MODE
Page 63
GAP2 FORMAT
LENGTH OF
22 Bytes
22 Bytes
22 Bytes
41 Bytes
FIELD
PORTION OF
WRITTEN BY
WRITE DATA
OPERATION
19 Bytes
38 Bytes
0 Bytes
0 Bytes
GAP 2
Rev. 02/02/2005