MT18D836 Micron Semiconductor Products, Inc., MT18D836 Datasheet

MT18D836

Manufacturer Part Number

MT18D836

Description

72-Pin DRAM Simms, Ecc Optimized, (x36), , Status: End of Life (EOL)

Manufacturer

Micron Semiconductor Products, Inc.

Datasheet

1.MT18D836.pdf (9 pages)

Current page: 1 of 9
Download datasheet (182Kb)

NOT RECOMMENDED FOR NEW DESIGNS

DRAM

MODULE

FEATURES

• Four-CAS#, ECC-optimized configuration in a 72-

• 16MB (4 Meg x 36) and 32MB (8 Meg x 36)

• High-performance CMOS silicon-gate process

• Single 5V ±10% power supply

• All inputs, outputs and clocks are TTL-compatible

• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#

• 2,048-cycle refresh distributed across 32ms

• FAST PAGE MODE (FPM) access

OPTIONS

• Timing

• Packages

KEY TIMING PARAMETERS

PART NUMBERS

GENERAL DESCRIPTION

accessed, 16MB and 32MB solid-state memories orga-

nized in a x36 configuration. These modules are de-

signed for systems that utilize ECC and do not conduct

single-byte accesses. These modules do not support

parity functionality.

addressed through 20 address bits that are entered 10

bits (A0-A9) at a time. RAS# is used to latch the first 10

bits and CAS#, the latter 10 bits. READ or WRITE cycles

are selected with the WE# input. A logic HIGH on WE#

dictates read mode, while a logic LOW on WE# dictates

4, 8 Meg x 36 ECC-Optimized DRAM SIMMs

DM84_2.p65 – Rev. 9/98

PART NUMBER

MT9D436M-x

MT9D436G-x

MT18D836M-x

MT18D836G-x

x = speed

SPEED

pin, single in-line memory module (SIMM)

(CBR) and HIDDEN

60ns access

72-pin SIMM

72-pin SIMM (Gold)

-6

The MT9D436 and MT18D836 are randomly

During READ or WRITE cycles, each bit is uniquely

110ns

CONFIGURATION FEATURES

4 Meg x 36

8 Meg x 36

60ns

RAC

35ns

30ns

4 CAS#, ECC

MARKING

15ns

CAC

-6

MODE

FPM

40ns

MT9D436

MT18D836

For the latest data sheet revisions, please refer to the

Micron Web site:

write mode. During a WRITE cycle, data-in (D) is latched

by the falling edge of WE# or CAS#, whichever occurs

last. EARLY WRITE occurs when WE# goes LOW prior to

CAS# going LOW, and the output pin(s) remain open

(High-Z) until the next CAS# cycle.

PAGE MODE

WRITE or READ-MODIFY-WRITE) within a row-ad-

dress-defined page boundary. The page cycle is al-

ways initiated with a row address strobed in by RAS#,

followed by a column address strobed in by CAS#. Ad-

ditional columns may be accessed by providing valid

column addresses, strobing CAS# and holding RAS#

LOW, thus executing faster memory cycles. Returning

*32MB version only

NOTE: Symbols in parentheses are not used on these

PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL

Page operations allow faster data operations (READ,

ECC-OPTIMIZED DRAM SIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

PIN ASSIGNMENT (Front View)

modules but may be used for other modules in

this product family. They are for reference only.

DQ19

DQ20

DQ21

DQ22

DQ1

DQ2

DQ3

DQ4

www.micron.com/datasheets

72-Pin SIMM

NC/RAS3#*

NC (A11)

RAS2#

DQ23

DQ24

DQ25

DQ26

DQ27

DQ5

DQ6

DQ7

DQ8

DQ9

A10

4, 8 MEG x 36

NC/RAS1#*

CAS0#

CAS2#

CAS3#

CAS1#

RAS0#

DQ18

DQ36

DQ10

DQ28

DQ11

DQ29

DQ12

DQ30

WE#

DQ13

DQ31

DQ14

DQ32

DQ33

DQ15

DQ34

DQ16

DQ35

DQ17

PRD1

PRD2

PRD3

PRD4

Related parts for MT18D836

MT18D836 Summary of contents

Page 1

... MT18D836G-x 8 Meg speed GENERAL DESCRIPTION The MT9D436 and MT18D836 are randomly accessed, 16MB and 32MB solid-state memories orga- nized in a x36 configuration. These modules are de- signed for systems that utilize ECC and do not conduct single-byte accesses. These modules do not support parity functionality ...

Page 2

... RAS# REFRESH cycle (RAS# ONLY, CBR or HIDDEN) so that all 2,048 combinations of RAS# addresses are ex- ecuted at least every 32ms, regardless of sequence. The CBR REFRESH cycle will invoke the refresh counter for automatic RAS# addressing. JEDEC-DEFINED PRESENCE-DETECT – MT18D836 (32MB) SYMBOL PIN PRD1 67 PRD2 ...

Page 3

NOT RECOMMENDED FOR NEW DESIGNS DQ1 DQ1 - 4 WE# U1 CAS# CAS0# RAS# RAS0# OE# A0–A10 11 CAS1# WE# DQ19 DQ1 - 4 WE# U6 CAS2# CAS# RAS2# RAS# A0–A10 OE# 11 CAS3# A0–A10 V U1- U1-U9 ...

Page 4

... DQ19 DQ1 - 4 WE# CAS# RAS3# RAS# OE# A0–A10 11 V U1-U18 DD V U1-U18 Meg x 36 ECC-Optimized DRAM SIMMs DM84_2.p65 – Rev. 9/98 FUNCTIONAL BLOCK DIAGRAM MT18D836 (32MB) DQ8 DQ9, 18, 27, 36 DQ1 - 4 DQ1 - 4 WE# WE CAS# CAS# RAS# RAS# A0–A10 A0–A10 OE# OE# ...

Page 5

NOT RECOMMENDED FOR NEW DESIGNS ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply Relative Operating Temperature, T (ambient) ... 0ºC to +70ºC A Storage Temperature (plastic) ............ -55ºC to +125ºC Power Dissipation ........................................................ 9W Short Circuit Output Current ...

Page 6

NOT RECOMMENDED FOR NEW DESIGNS CAPACITANCE PARAMETER Input Capacitance: A0-A10 Input Capacitance: WE# Input Capacitance: RAS0#-RAS3# Input Capacitance: CAS0#-CAS3# Input/Output Capacitance: DQ1-DQ36 AC ELECTRICAL CHARACTERISTICS (Notes: 5-12 +5V ±10 CHARACTERISTICS PARAMETER Access time from column address ...

Related keywords

MT18D836 datasheet
MT18D836 data sheet
MT18D836 pdf datasheet
MT18D836 component
MT18D836 part
MT18D836 distributor
MT18D836 RoHS
MT18D836 datasheet download

MT18D836 Micron Semiconductor Products, Inc., MT18D836 Datasheet

MT18D836

Related parts for MT18D836

MT18D836 Summary of contents

Page 1

Page 2

Page 3

Page 4

Page 5

Page 6

Page 7

Page 8

Page 9

Related keywords