MT28C3224P18 Micron Semiconductor Products, Inc., MT28C3224P18 Datasheet

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... Dual 64-bit chip protection registers for security purposes 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_4.p65 – Rev. 4, Pub. 10/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 256K x 16 SRAM COMBO MEMORY MT28C3224P20 MT28C3224P18 Low Voltage, Extended Temperature 0.18µm Process Technology ...

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... GENERAL DESCRIPTION The MT28C3224P20 and MT28C3224P18 combi- nation Flash and SRAM memory devices provide a com- pact, low-power solution for systems where PCB real estate premium. The dual-bank Flash devices are high-performance, high-density, nonvolatile memory with a revolutionary architecture that can sig- nificantly improve system performance ...

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... P = Asynchronous/Page Read PART NUMBER MT28C3224P20FL-80 BET MT28C3224P20FL-80 TET MT28C3224P18FL-85 BET MT28C3224P18FL-85 TET 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory MT28C3224P20_4.p65 – Rev. 4, Pub. 10/02 256K x 16 SRAM COMBO MEMORY Valid combinations of features and their correspond- ing part numbers are listed in Table 2. ...

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F_WE# F_OE# F_CE# F_RP# – A18 A20 – A0 A17 S_CE1# S_CE2 S_OE# S_WE# DQ0-DQ15 Data Input Buffer F_RST# F_CE# CSM F_WE# F_OE# WSM I/O Logic Address Input A0–A20 Buffer Address Latch 2 Meg x 16 Page Flash 256K x ...

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BALL DESCRIPTIONS 66-BALL FBGA NUMBERS SYMBOL TYPE H6, G9, G8, G7, A0–A20 Input H5, H4, G6, G5, B4, B6, B5, A4, A8, A7, A6, A5, B3, G4, G3, E5 F_CE# Input H9 F_OE# Input C3 F_WE# Input D4 ...

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BALL DESCRIPTIONS (continued) 66-BALL FBGA NUMBERS SYMBOL TYPE E4 F_V Input/ PP Supply D10, H3 F_V Supply CC A9, H8 F_V Supply SS D9 S_V Supply CC D3 S_V Supply SS A10 V Q Supply CC A1, A2, A11, NC ...

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TRUTH TABLE – FLASH FLASH SIGNALS MODES F_RP# F_CE# F_OE# F_WE# S_CE1# S_CE2 S_OE# S_WE# S_UB# S_LB# Read Write Standby Output Disable Reset TRUTH TABLE ...

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Bank b = 24Mb Block Block Size (K-bytes/K-words) 70 64/32 69 64/32 68 64/32 67 64/32 66 64/32 65 64/32 64 64/32 63 64/32 62 64/32 61 64/32 60 64/32 59 64/32 58 64/32 57 64/32 56 64/32 55 64/32 ...

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Bank a = 8Mb Block Block Size (K-bytes/K-words) 70 8/4 69 8/4 68 8/4 67 8/4 66 8/4 65 8/4 64 8/4 63 8/4 62 64/32 61 64/32 60 64/32 59 64/32 58 64/32 57 64/32 56 64/32 55 64/32 ...

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FLASH MEMORY OPERATING MODES COMMAND STATE MACHINE Commands are issued to the command state ma- chine (CSM) using standard microprocessor write tim- ings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). The ...

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I/Os (DQ0–DQ7) need to be interpreted. Address lines select the status register pertinent to the selected memory partition. Register data is updated and latched on the falling edge of F_OE# or F_CE#, whichever occurs last. Latch- ing the data ...

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CODE DEVICE MODE BUS CYCLE 10h Alt. Program Setup First 20h Erase Setup First 40h Program Setup First 50h Clear Status First Register 60h Protection First Configuration Setup 70h Read Status First Register 90h Read Protection First Configuration 98h Read ...

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Command Descriptions (continued) CODE DEVICE MODE BUS CYCLE D0h Erase Confirm Second Program/Erase First Resume FFh Read Array First 01h Lock Block Second 2Fh Lock Down Second D0h Unlock Block Second 00h Invalid/Reserved 2 Meg x 16 Page Flash 256K ...

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CLEAR STATUS REGISTER The internal circuitry can set, but not clear, the block lock status bit (SR1), the V status bit (SR3), the pro- PP gram status bit (SR4), and the erase status bit (SR5) of the status register. The ...

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PROGRAMMING OPERATIONS There are two CSM commands for programming: PROGRAM SETUP and ALTERNATE PROGRAM SETUP (see Table 3). After the desired command code is entered (10h or 40h command code on DQ0–DQ7), the WSM takes over and correctly sequences the ...

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WSMS ESS 7 6 STATUS BIT # STATUS REGISTER BIT SR7 WRITE STATE MACHINE STATUS (WSMS) Check write state machine bit first to determine word 1 = Ready 0 = Busy SR6 ERASE SUSPEND STATUS (ESS BLOCK ERASE ...

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Figure 4 Automated Word Programming Flowchart Start Issue PROGRAM SETUP Command and Word Address Issue Word Address and Word Data Read Status Register Bits NO NO PROGRAM SR7 = 1? SUSPEND? YES Full Status Register 1 Check (optional) Word Program ...

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Figure 5 PROGRAM SUSPEND/ PROGRAM RESUME Flowchart Start Issue PROGRAM SUSPEND Command Read Status Register Bits NO SR7 = 1? YES NO SR2 = 1? YES Issue READ ARRAY Command NO Finished Reading ? YES Issue PROGRAM RESUME Command PROGRAM ...

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Figure 6 BLOCK ERASE Flowchart Start Issue ERASE SETUP Command and Block Address Issue BLOCK ERASE CONFIRM Command and Block Address Read Status Register Bits NO NO ERASE SUSPEND? YES Full Status Register 1 Check (optional) ...

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Figure 7 ERASE SUSPEND/ERASE RESUME Flowchart Start Issue ERASE SUSPEND Command Read Status Register Bits NO SR7 = 1? YES NO SR6 = 1? YES READ or PROGRAM? READ Issue READ ARRAY Command READ or NO PROGRAM Complete? YES Issue ...

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... MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY BLOCK LOCKING The Flash memory of the MT28C3224P20 and MT28C3224P18 devices provide a flexible locking scheme which allows each block to be individually locked or unlocked with no latency. The devices offer two-level protection for the blocks. ...

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F_WP# DQ1 DQ0 Unlocked Locked (Default Lock Down Unlocked Lock Down Disabled Lock Down Disabled The LOCK DOWN function ...

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READ ARRAY command, FFh, must be issued to the bank containing address 00h prior to issuing other commands. LOCKING OPERATIONS DURING ERASE SUSPEND Changes to block lock status can be performed dur- ing an ERASE SUSPEND ...

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STANDBY MODE Icc supply current is reduced by applying a logic HIGH level on F_CE# and F_RP# to enter the standby mode. In the standby mode, the outputs are placed in High-Z. Applying a CMOS logic HIGH level on F_CE# ...

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... Storage Temperature Range ................. -55 Soldering Cycle ........................................... 260 RECOMMENDED OPERATING CONDITIONS PARAMETER Operating temperature V supply voltage (MT28C3224P18 supply voltage (MT28C3224P20) CC I/O supply voltage (MT28C3224P18) I/O supply voltage (MT28C3224P20) V voltage (when used as logic control in-factory programming voltage PP Data retention supply voltage Block erase cycling (V ) ...

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COMBINED DC CHARACTERISTICS DESCRIPTION Input Low Voltage Input High Voltage Output Low Voltage I = 100µA (Flash) OL Output Low Voltage I = 100µA (SRAM) OL Output High Voltage I = -100µA (Flash) OH Output High Voltage I = -100µA ...

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COMBINED DC CHARACTERISTICS (continued) DESCRIPTION S_V Read/Write Operating CC Supply Current – Page Access Mode V Current PP (Read, Standby, Erase Suspend, Program Suspend) NOTE: 1. All currents are in RMS unless otherwise noted may decrease to -0.4V ...

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CAPACITANCE (T = +25º MHz) A PARAMETER/CONDITION Input Capacitance Output Capacitance FLASH READ CYCLE TIMING REQUIREMENTS PARAMETER Address to output delay CE# LOW to output delay Page address access OE# LOW to output delay F_RP# HIGH to ...

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FLASH WRITE CYCLE TIMING REQUIREMENTS PARAMETER Reset HIGH recovery to WE# going LOW CE# setup to WE# going LOW Write pulse width Data setup to WE# going HIGH Address setup to WE# going HIGH CE# hold from WE# HIGH Data ...

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TWO-CYCLE PROGRAMMING/ERASE OPERATION V IH A0–A20 High-Z DQ0–DQ15 RST WP ...

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SINGLE ASYNCHRONOUS READ OPERATION V IH A0–A20 High-Z DQ0–DQ15 RP READ TIMING PARAMETERS -80 V ...

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ASYNCHRONOUS PAGE MODE READ OPERATION V IH A2–A20 A0– F_CE F_OE F_WE DQ0–DQ15 F_RP ...

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V IH F_CE F_RST F_OE DQ0–DQ15 V OL READ TIMING PARAMETERS - 1.80V–2.20V SYMBOL MIN MAX t RWH 200 t RP 100 2 ...

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OFFSET DATA 00 2Ch Manufacturer Code 01 B4h Top boot block device code B5h Bottom boot block device code 02–0F reserved Reserved 10, 11 0051,0052 “QR” 12 0059 “Y” 13, 14 0003, 0000 Primary OEM command set 15, 16 0039, ...

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OFFSET DATA 37, 38 0020, 0000 Top boot block device……64KB 0000, 0001 Bottom boot block device……64KB 39, 3A 0050, 0052 “PR” 3B 0049 “I” 3C 0030 Major version number, ASCII 3D 0031 Minor version number, ASCII 3E 00E6 Optional Feature ...

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SRAM OPERATING MODES SRAM READ ARRAY The operational state of the SRAM is determined by S_CE1#, S_CE2, S_WE#, S_OE#, S_UB#, and S_LB#, as indicated in the Truth Table. To perform an SRAM READ operation, S_CE1#, and S_OE#, must be at ...

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TIMING TEST CONDITIONS Input pulse levels .................... 0.1V V Input rise and fall times .................................... 5ns Input timing reference levels ......................... 0.5V Output timing reference levels ..................... 0.5V Operating Temperature ............... -40 NOTE: For input/output contacts, refer to the Capacitance ...

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S_OE ADDRESS DATA-OUT ADDRESS S_CE1# S_CE2 S_OE# S_LB#, S_UB# DATA-OUT READ TIMING PARAMETERS -80/- 1.70V–1.90V SYMBOL MIN MAX t RC 100 t AA 100 t CO 100 ...

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ADDRESS S_CE1# S_CE2 S_LB#, S_UB# S_WE# DATA-IN DATA-OUT WRITE TIMING PARAMETERS SYMBOL MIN LBW, UBW Meg x 16 Page Flash 256K x 16 SRAM Combo ...

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ADDRESS S_CE1# S_LB#, S_UB# S_WE# DATA-IN DATA-OUT WRITE TIMING PARAMETERS SYMBOL MIN LBW, UBW Meg x 16 Page Flash 256K x 16 SRAM Combo Memory ...

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SEATING PLANE C C 0.10 66X Ø 0.35 BALL A12 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE- REFLOW DIAMETER IS Ø 0.33 2.80 ±0.05 5.60 4.40 ±0.05 12.00 ±0.10 NOTE: 1. All dimensions in millimeters. ...

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REVISION HISTORY Rev. 4 ................................................................................................................................................................................ 10/02 • ADVANCE designation removed. Rev. 3, ADVANCE .............................................................................................................................................................. 7/02 • Updated Status Register Section • Updated command descriptions • Updated Read-While-Write Concurrency section • Updated timing diagrams • Changed Cout from 9 (TYP) and ...