MT54W1MH18B Micron Semiconductor Products, Inc., MT54W1MH18B Datasheet
MT54W1MH18B
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MT54W1MH18B Summary of contents
Page 1
... Operating Temperature Range Commercial (0°C £ T £ +70°C) A NOTE : 1. A Part Marking Guide for the FBGA devices can be found on Micron’s Web site—http://www.micron.com/numberguide. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG MT54W2MH8B II SRAM MT54W1MH18B MT54W512H36B Table 1: PART NUMBER MT54W2MH8BF-xx DD ...
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... V , HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V READ cycles are pipelined. The request is initiated by asserting R# LOW at K rising edge. Data is delivered after the next rising edge of the next 1), using C and C# as the output timing references ...
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... Circuitry 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V automatically resets the DLL when the absence of input clock is detected. See Micron Technical Note TN- 54-02 for more information on clock DLL start-up pro- cedures ...
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... For 2 Meg 20 NWx separate nibble writes. For 1 Meg 18; BWx separate byte writes. For 512K 36; BWx separate byte writes. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 2: Functional Block Diagram 2 Meg Meg x 18; 512K ...
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... For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 3: Application Example SRAM # 250Ω ...
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... TDO TCK NOTE : 1. Expansion address: 2A for 72Mb 2. NW1# controls writes to D4:D7 3. Expansion address: 7A for 144Mb 4. Expansion address: 10A for 36Mb 5. Expansion address: 5B for 288Mb 6. NW0# controls writes to D0:D3 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. NW1 ...
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... TCK NOTE : 1. Expansion address: 2A for 144Mb 2. Expansion address: 3A for 36Mb 3. BW1# controls writes to D9:D17 4. Expansion address: 7A for 288Mb 5. Expansion address: 10A for 72Mb 6. BW0# controls writes to D0:D8 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. BW1 ...
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... Expansion address is 3A for 72Mb 3. BW2# controls writes to D18:D26 4. BW1# controls writes to D9:D17 5. Expansion address is 9A for 36Mb 6. Expansion address is 10A for 144Mb 7. BW3# controls writes to D27:D35 8. BW0# controls writes to D0:D8 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. ...
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... See Ball Layout figures for ball site location of individual signals. The x8 device uses Q0:Q7. Remaining signals are NC. The x18 device uses Q0:Q17. Remaining signals are NC. The x36 device uses Q0:Q35. Remaining signals are NC. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X X 1.8V V ...
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... Power Supply: GND – No Connect: These balls are internally connected to the die, but have no function and may be left not connected to the board to minimize ball count. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG HSTL, QDRIIb2 SRAM DD DESCRIPTION Micron Technology, Inc ...
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... Bus cycle is terminated at the end of this sequence (burst count = 2). 2. State transitions (R# = LOW (W# = LOW). 3. Read and write state machines can be simultaneously active. 4. State machine, control timing sequence is controlled by K. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 4: Bus Cycle State Diagram RD RD ...
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... This table illustrates operation for x18 devices. The x36 device operation is similar, except for the addition of BW2# (controls D18:D26) and BW3# (controls D27:D35). The x8 operation is similar, except that NW0# controls D0:D3, and NW1# controls D4:D7. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. ...
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... Notes appear following parameter tables on page 16; 0°C £ T DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to ..... -0.5V to +2.8V SS the device ...
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... Output Capacitance (Q) Clock Capacitance Table 12: Thermal Resistance Note 13; notes appear following parameter tables on page 16 DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Balls (Bottom) 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V £ +70° SYM TYP ³ Cycle IL ...
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... Control inputs valid to K rising edge Data-in valid rising edge Hold Times K rising edge to address hold K rising edge to control inputs hold K, K# rising edge to data-in hold 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. SYMBOL MIN MAX MIN MAX t 4 ...
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... Typical values are measured at V 1.5V, and temperature = 25°C. 11. NOP currents are valid when entering NOP after all pending READ and WRITE cycles are com- pleted. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1. 12. Average I/O current and power is provided for OH informational purposes only and is not tested ...
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... Input rise and fall times . . . . . . . . . . . . . . . . . . . . 0.7ns Input timing reference levels . . . . . . . . . . . . . . . . 0.75V Output reference levels . . . . . . . . . . . . . . . . . . .V ZQ for 50 W impedance . . . . . . . . . . . . . . . . . . . . . 250 W Output load . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 5 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. HSTL, QDRIIb2 SRAM DD Output Load Equivalent ...
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... Outputs are disabled (High-Z) one clock cycle after a NOP this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. (This note applies to whole diagram.) 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 6: READ/WRITE Timing WRITE ...
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... The 0/1 next to each state represents the value of TMS at the rising edge of TCK. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK ...
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... Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Shift-DR state. The EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions can be used to capture the contents of the I/O ring. ...
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... SAMPLE/PRELOAD SAMPLE/PRELOAD is a 1149.1 mandatory instruc- tion. The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1-compliant. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG HSTL, QDRIIb2 SRAM DD Note that since the PRELOAD part of the command ...
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... CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 10. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG X 1.8V V Figure 9: TAP Timing THTL ...
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... This table defines DC values for TAP control and data balls only. The DQ SRAM balls used in JTAG operation will have the DC values as defined in Table 8, “DC Electrical Characteristics and Operating Conditions,” on page 13. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V TAP AC Output Load Equivalent to 1.8V ...
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... Do Not Use: This instruction is reserved for future use. BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V DESCRIPTION 000 Revision number. def = 001 for 18Mb density for x36 width ...
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... V , HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 8, 1 MEG X 1. HSTL, QDRIIb2 SRAM DD BIT# FBGA BALL 37 10D 10C 40 11D 11B 44 11C 10B ...
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... S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of of Micron Technology, Inc. 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG 1.8V V Figure 11: 165-Ball FBGA 0.12 C ...
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... Rev. 3, Pub. 12/01, ADVANCE .......................................................................................................................................12/01 • Changed AC timing Rev. 2, Pub. 11/01, ADVANCE .......................................................................................................................................11/01 • New ADVANCE data sheet 18Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W1MH18B_H.fm – Rev. H, Pub. 3/03 2 MEG X 1.8V V test conditions for read to write ratio DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...