MT28C6428P20 Micron Semiconductor Products, Inc., MT28C6428P20 Datasheet - Page 11

• Manufacturer Part Number: MT28C6428P20
• Description: 4 Meg X 16 Asynchronous/page Flash 512K X 16 SRAM Combo Memory
• Manufacturer: Micron Semiconductor Products, Inc.

edge of F_OE# or F_CE#, whichever occurs last. The
latest falling edge of either of these two signals up-
dates the latch within a given READ cycle. Latching the
data prevents errors from occurring if the register input
changes during a status register read.
WSM to the external microprocessor. During periods
when the WSM is active, the status register can be polled
to determine the WSM status. Table 8 defines the sta-
tus register bits.
PROGRAM/ERASE operation, the data appearing on
DQ0–DQ7 remains as status register data until a new
command is issued to the CSM. To return the device to
other modes of operation, a new command must be
issued to the CSM.
NOTE: 1. BA:
4 Meg x 16 Asynchronous/Page Flash 512K x 16 SRAM Combo Memory
MT28C6428P20_3.p65 – Rev. 3, Pub. 7/02
COMMAND
READ ARRAY
READ PROTECTION CONFIGURATION REGISTER
READ STATUS REGISTER
CLEAR STATUS REGISTER
READ QUERY
BLOCK ERASE SETUP
PROGRAM SETUP
ACCELERATED PROGRAMMING ALGORITHM (APA)
PROGRAM/ERASE SUSPEND
PROGRAM/ERASE RESUME – ERASE CONFIRM
LOCK BLOCK
UNLOCK BLOCK
LOCK DOWN BLOCK
CHECK BLOCK ERASE
PROTECTION REGISTER PROGRAM
PROTECTION REGISTER LOCK
ENABLE/DISABLE DEEP POWER-DOWN
Register data is updated and latched on the falling
The status register provides the internal state of the
After monitoring the status register during a
DPW:BBCFh = Disable deep power-down
IA:
ID:
LPA: Lock protection register address
PA:
PD:
QA: Query code address
QD: Query code data
SRD: Data read from the status register
WA: Word address of memory location to be written, or read
WD: Data to be written at the location WA
X:
Address within the block
BBDFh = Enable deep power-down
Identification code address
Identification code data
Protection register address
Data to be written at location PA
“Don’t Care”
Command Definitions
4 MEG x 16 ASYNCHRONOUS/PAGE FLASH
OPERATION ADDRESS
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
Table 4
11
FIRST BUS CYCLE
512K x 16 SRAM COMBO MEMORY
COMMAND STATE MACHINE OPERATIONS
listed in Table 3. The 8-bit command code is input to
the device on DQ0–DQ7 (see Table 4 for command
definitions). During a PROGRAM or ERASE cycle, the
CSM informs the WSM that a PROGRAM or ERASE cycle
has been requested.
program sequences and the CSM responds to a PRO-
GRAM SUSPEND command only.
ERASE SUSPEND command only. When the WSM has
completed its task, the WSMS bit (SR7) is set to a logic
HIGH level and the CSM responds to the full command
set. The CSM stays in the current command state until
the microprocessor issues another command.
GRAM operation only when F_V
voltage range.
DPW
LPA
WA
WA
WA
QA
BA
BA
BA
BA
BA
BA
BA
BA
BA
PA
IA
The CSM decodes instructions for the commands
During a PROGRAM cycle, the WSM controls the
During an ERASE cycle, the CSM responds to an
The WSM successfully initiates an ERASE or PRO-
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DATA
40h
D0h
FFh
90h
70h
50h
98h
20h
10h
B0h
60h
60h
60h
20h
C0h
C0h
60h
OPERATION ADDRESS
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
WRITE
READ
READ
READ
SECOND BUS CYCLE
PP
is within its correct
DPW
LPA
WA
WA
QA
BA
BA
BA
BA
BA
PA
IA
X
©2002, Micron Technology, Inc.
ADVANCE
1
DATA
FFFDh
SRD
D0h
D0h
D1h
WD
WD
01h
2Fh
03h
QD
PD
ID
1