MT57V256H36E Micron Semiconductor Products, Inc., MT57V256H36E Datasheet - Page 2

• Manufacturer Part Number: MT57V256H36E
• Description: 9Mb DDR SRAM 2.5V Vdd, HSTL Pipelined
• Manufacturer: Micron Semiconductor Products, Inc.

enhance pipelined WRITE cycles and reduce READ-to-
WRITE turnaround time. WRITE cycles are self-timed.
loops and can therefore be placed into a stopped-clock
state to minimize power without lengthy restart times.
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 2.5V I/O levels to shift data
during this testing mode of operation.
ing an appropriate reference voltage (V
device is ideally suited for applications requiring very
rapid data transfer by operation in data-doubled
mode. The device is also ideal in applications requiring
the cost benefits of pipelined CMOS SRAMs and the
reduced READ-to-WRITE turnaround times of Late
Write SRAMs.
all inputs and outputs are HSTL-compatible. The
device is ideally suited for cache, network, telecom,
DSP , and other applications that benefit from a very
wide, high-speed data bus.
NOTE:
256K x 36 2.5V V
MT57V256H36E_16_B.fm - Rev. B, Pub. 1/03
1. SA0 and SA1 are advanced in linear burst order at each K and K# rising edge.
2. The compare width is a 16-bits. The compare is performed only if a WRITE is pending and a READ cycle is requested.
3. The functional block diagram illustrates simplified device operation. See truth tables, ball descriptions, and timing
4. CQ and CQ# do not tri-state except during some JTAG test modes.
Additional write registers are incorporated to
The device does not utilize internal phase-locked
Four balls are used to implement JTAG test capabili-
The device can be used in HSTL systems by supply-
The SRAM operates from a +2.5V power supply, and
If the address matches, data is routed directly to the device outputs, bypassing the memory array.
diagrams for detailed information.
SA0, SA1, SA
R/W#
DD
LD#
, HSTL, Pipelined DDR SRAM
K#
K
18
36
36
E
E
E
REGISTER
REGISTER
ADDRESS
REGISTER
ADDRESS
E
E
REGISTER
REGISTER
WRITE
R/W#
INPUT
INPUT
COMPARE
18
(NOTE 2)
36
WRITE#
36
SA0''’
Functional Block Diagram: 256K x 36
SA0’
SA0#’
SA0’
SA0#’
SA0’
0
1
18
CLK
36
CLK
36
36
SA0
SA1
D1
D0
REGISTER
WRITE
C
BURST
LOGIC
(NOTE 1)
16
18
REGISTER
REF
Q1
Q0
36
OE
36
SA0’
SA1’
). The
0.16µm Process
DRIVER
WRITE
18
18
Figure 2:
2.5V V
36
36
WRITE#
READ
WRITE#
128K x 72
MEMORY
2
ARRAY
sramds) for the latest data sheet.
DDR Operation
tion through high-clock frequencies (achieved through
pipelining) and double data rate mode of operation. At
slower frequencies, the DDR SRAM requires a single
NO OPERATION (NOP) cycle when transitioning from
a READ to a WRITE cycle. At higher frequencies, a sec-
ond NOP cycle may be required to prevent bus conten-
tion. NOP cycles
a WRITE to a READ.
data for the WRITE are stored in registers. The write
information must be stored because the SRAM cannot
perform the last WORD WRITE to the array without
conflicting with the READ. The data stays in this regis-
ter until the next WRITE cycle occurs. On the first
WRITE cycle after the READ(s), the stored data from
the earlier WRITE will be written into the SRAM array.
This is called a POSTED WRITE.
SA1’-SA17’
SA0''
DD
36
36
Please refer to Micron’s Web site
The DDR SRAM enables high performance opera-
If a READ occurs after a WRITE cycle, address and
SENSE
AMPS
Micron Technology, Inc., reserves the right to change products or specifications without notice.
, HSTL, PIPELINED DDR SRAM
C#
C
C
36
36
CONTROL
OUTPUT
LOGIC
REGISTER
OUTPUT
a
re not required when switching from
36
36
SA0'''
MUX
2:1
0
1
36
36
36
OUTPUT
BUFFER
ZQ
(www.micron.com/
E
256K x 36
©2003, Micron Technology Inc.
36
ADVANCE
(Note 4)
DQ
CQ, CQ#