MT58L128L18D Micron Semiconductor Products, Inc., MT58L128L18D Datasheet

MT58L128L18D

Manufacturer Part Number

MT58L128L18D

Description

2Mb Syncburst SRAM, 3.3V Vdd, 3.3V I/O, Pipelined, Dcd,

Manufacturer

Micron Semiconductor Products, Inc.

Datasheet

1.MT58L128L18D.pdf (19 pages)

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Part Number:

MT58L128L18DT-10A

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NOT RECOMENDED FOR NEW DESIGNS

2Mb SYNCBURST

SRAM

FEATURES

• Fast clock and OE# access times

• Single +3.3V +0.3V/-0.165V power supply (V

• Separate +3.3V isolated output buffer supply

• SNOOZE MODE for reduced-power standby

• Common data inputs and data outputs

• Individual BYTE WRITE control and GLOBAL

• Three chip enables for simple depth expansion and

• Clock-controlled and registered addresses, data

• Internally self-timed WRITE cycle

• Burst control pin (interleaved or linear burst)

• Automatic power-down

• 100-pin TQFP package

• Low capacitive bus loading

• x18, x32, and x36 options available

OPTIONS

• Timing (Access/Cycle/MHz)

• Configurations

• Packages

• Operating Temperature Range

GENERAL DESCRIPTION

high- speed, low-power CMOS designs that are fabri-

cated using an advanced CMOS process.

18, 64K x 32, or 64K x 36 SRAM core with advanced

synchronous peripheral circuitry and a 2-bit burst

counter. All synchronous inputs pass through registers

2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM

MT58L128L18D_C.p65 – Rev. C, Pub. 11/02

WRITE

address pipelining

I/Os and control signals

3.5ns/6ns/166 MHz

4.0ns/7.5ns/133 MHz

5ns/10ns/100 MHz

128K x 18

100-pin TQFP

Commercial (0°C to +70°C)

The Micron

Micron’s 2Mb SyncBurst SRAMs integrate a 128K x

64K x 32

64K x 36

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

MT58L128L18DT-10

SyncBurst

Part Number Example:

™

SRAM family employs

MT58L128L18D

MT58L64L32D

MT58L64L36D

MARKING

None

-7.5

™

-10

-6

)

PIPELINED, DCD SYNCBURST SRAM

MT58L128L18D, MT58L64L32D,

MT58L64L36D

3.3V V

Deselect

controlled by a positive-edge-triggered single clock

input (CLK). The synchronous inputs include all ad-

dresses, all data inputs, active LOW chip enable (CE#),

two additional chip enables for easy depth expansion

(CE2, CE2#), burst control inputs (ADSC#, ADSP#,

ADV#), byte write enables (BWx#) and global write

(GW#).

(OE#), clock (CLK) and snooze enable (ZZ). There is also

a burst mode pin (MODE) that selects between inter-

leaved and linear burst modes. The data-out (Q), en-

abled by OE#, is also asynchronous. WRITE cycles can

be from one to two bytes wide (x18) or from one to four

bytes wide (x32/x36), as controlled by the write control

inputs.

status processor (ADSP#) or address status controller

(ADSC#) input pins. Subsequent burst addresses can be

internally generated as controlled by the burst advance

pin (ADV#).

simplify WRITE cycles. This allows self-timed WRITE

cycles. Individual byte enables allow individual bytes

to be written. During WRITE cycles on the x18 device,

BWa# controls DQa pins and DQPa; BWb# controls

DQb pins and DQPb. During WRITE cycles on the x32

and x36 devices, BWa# controls DQa pins and DQPa;

BWb# controls DQb pins and DQPb; BWc# controls

*JEDEC-standard MS-026 BHA (LQFP).

Asynchronous inputs include the output enable

Burst operation can be initiated with either address

Address and write control are registered on-chip to

2Mb: 128K x 18, 64K x 32/36

, 3.3V I/O, Pipelined, Double-Cycle

100-Pin TQFP*

Related parts for MT58L128L18D

MT58L128L18D Summary of contents

Page 1

... All synchronous inputs pass through registers 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM ™ ...

Page 2

... CE2# OE# NOTE: Functional Block Diagrams illustrate simplified device operation. See truth table, pin descriptions and timing diagrams for detailed information. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM FUNCTIONAL BLOCK DIAGRAM 128K ...

Page 3

... Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM Micron’s 2Mb SyncBurst SRAMs operate from a +3 ...

Page 4

... Connect (NC) is used on the x32 version. Parity (DQPx) is used on the x36 version. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM PIN ASSIGNMENT (Top View) 100-Pin TQFP ...

Page 5

... ADV# 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM TYPE SA0 Input Synchronous Address Inputs: These inputs are registered and must SA1 meet the setup and hold times around the rising edge of CLK. ...

Page 6

... NC/SA 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM TYPE Input Synchronous Address Status Processor: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ is performed using the new address, independent of the byte write enables and ADSC#, but dependent upon CE#, CE2, and CE2# ...

Page 7

... WRITE All Bytes WRITE All Bytes NOTE: Using BWE# and BWa# through BWd#, any one or more bytes may be written. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM THIRD ADDRESS (INTERNAL) X ...

Page 8

... BWE# LOW or GW# LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM ZZ ADSP# ADSC# ADV# WRITE# OE# ...

Page 9

... V Q should never exceed V DD 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM *Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional ...

Page 10

... Typical values are measured at 3.3V, 25°C, and 10ns cycle time. 4. This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM SYMBOL MIN ...

Page 11

... Test conditions follow standard test methods (Junction to Ambient) Thermal Resistance (Junction to Top of Case) NOTE: 1. This parameter is sampled. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM CONDITIONS and procedures for measuring thermal impedance, per EIA/JESD51. 11 ...

Page 12

... Chip enable must be valid at each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM -6 ...

Page 13

... The Micron 128K x 18, 64K x 32, and 64K x 36 SyncBurst SRAM timing is dependent upon the capaci- tive loading on the outputs. Consult the factory for copies of I/O current versus voltage curves. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM = (V /2. ...

Page 14

... I ISB2Z ALL INPUTS (except ZZ) Outputs (Q) 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM The ZZ pin is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When the ZZ pin becomes a logic HIGH, I ...

Page 15

... Timing is shown assuming that the device was not enabled before entering into this sequence. OE# does not cause driven until after the following clock rising edge. 4. Outputs are disabled within two clock cycles after deselect. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM READ TIMING t ADSS ...

Page 16

... Full-width WRITE can be initiated by GW# LOW; or GW# HIGH and BWE#, BWa# and BWb# LOW for x18 device; or GW# HIGH and BWE#, BWa#-BWd# LOW for x32 and x36 devices. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM WRITE TIMING ...

Page 17

... The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed. 4. GW# is HIGH. 5. Back-to-back READs may be controlled by either ADSP# or ADSC#. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM READ/WRITE TIMING A3 ...

Page 18

... E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, SyncBurst, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 PIPELINED, DCD SYNCBURST SRAM 100-PIN PLASTIC TQFP (JEDEC LQFP) 0.625 14.00 ± ...

Page 19

... Changed heading on Mechanical Drawing from BGA to FBGA Added 165-Pin FBGA package, REV 3/00, FINAL ....................................................................................... May/23/00 Added PRELIMINARY PACKAGE DATA to diagram 2Mb: 128K x 18, 64K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L128L18D_C.p65 – Rev. C, Pub. 11/02 2Mb: 128K x 18, 64K x 32/36 PIPELINED, DCD SYNCBURST SRAM 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

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