MT90401 Zarlink Semiconductor, MT90401 Datasheet - Page 24

• Manufacturer Part Number: MT90401
• Description: Sonet/sdh System Synchronizer
• Manufacturer: Zarlink Semiconductor

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When the same ten Normal to Holdover to Normal mode changes occur with TIE disabled, the overall MTIE will
only be 250ns. There would be no accumulated phase change, since the input to output phase is re-aligned after
every Holdover to Normal state change.
5.3
The MT90401 provides a 155.52MHz clock that is frequency locked to the internally generated 19.44MHz clock.
The locking of both clocks is achieved by the internal analog PLL that multiplies the 19.44MHz clock eight times.
This C155 clock is output on pins C155P and C155N in LVDS format. The LVDS offset voltage Vos is set by
applying an external 1.25V reference voltage to the Vref input (pin 33). This pin can be connected to a common
1.25V voltage reference that may exist on the customer board or alternatively can be generated by a simple voltage
divider as it is shown in Figure 13 - LVDS Voltage Offset Vos Generation Circuit. To ensure proper operation of
LVDS drivers, the decoupling capacitor must be placed very close to the MT90401 package.
5.4
If the HW pin is tied low, an 8 bit Motorola microprocessor may be used to control the PLL and report on the device
status. In this case the control pins SONET/SDH, RSEL, MS1, MS2, FS1, FS2, and FLOCK are unused and they
are replaced by the control bits SONET/SDH, RSEL, MS1, MS2, FS1, FS2, FLOCK. The input pin PCCi remains in
use. The output pins LOCK, HOLDOVER, SECOOR, PRIOOR function whether the device is in microprocessor
mode or hardware mode, but these signals are also available in Status Register 1. The microport provides
additional functionality not available in hardware.
0.02ppm is the accuracy of Holdover Mode
50ns is the maximum phase continuity of the MT90401 from Normal Mode to Holdover Mode
200ns is the maximum phase continuity of the MT90401 from Holdover Mode to Normal Mode (with or
without TIE Corrector Circuit)
C155 clock generation and LVDS output drivers
Microport
Figure 13 - LVDS Voltage Offset Vos Generation Circuit
Phase hold
Phase state
Phase 10
Zarlink Semiconductor Inc.
=
=
=
10
MT90401
0.02ppm
50ns
250ns
24
+
200ns
+
2s
40ns
=
=
250ns
40ns
=
2.9us
Data Sheet