MT90401 Zarlink Semiconductor, MT90401 Datasheet - Page 4

• Manufacturer Part Number: MT90401
• Description: Sonet/sdh System Synchronizer
• Manufacturer: Zarlink Semiconductor

Pin Description (continued)
Pin #
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
PRIOOR
C155N,
C155P
Name
VREF
C1.5o
C19o
V
V
V
V
V
SEC
V
Tms
FS2
FS1
Tdo
Tclk
Trst
PRI
Tdi
C6
IC
IC
SS2
SS3
DD2
SS4
SS5
DD
Secondary Reference (Input).
(falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz,
2.048MHz or 19.44MHz) may be used. In hardware mode the selection of the input
reference is based upon the MS1, MS2 and RSEL control inputs.
Primary Reference (Input).
(falling edge) used for synchronization. One of four possible frequencies (8kHz, 1.544MHz,
2.048MHz or 19.44MHz) may be used. In hardware mode the selection of the input
reference is based upon the MS1, MS2 and RSEL control inputs.
Digital ground. 0 Volts
Internal Connection. Leave unconnected
Analog ground. 0 Volts
Positive Analog Power Supply. Analog supply.
Positive Power Supply. Digital supply.
LVDS 155.52 MHz (Output)). Differential outputs generating a 155.52MHz clock
Digital ground. 0 Volts
LVDS Reference Voltage (Input).
IEEE 1149.1a Test Data Output (Output). If not used, this pin should be left unconnected.
IEEE 1149.1a Test Mode Selection (Input). If not used, this pin should be pulled high.
IEEE 1149.1a Test Clock Signal (Input). If not used, this pin should be pulled high.
IEEE 1149.1a Reset Signal (Input). If not used, this pin should be held low.
IEEE 1149.1a Test Data Input (Input). If not used, this pin should be pulled high.
Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four
possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI
and SEC inputs. For more details see FS2 bit description in Table 6 - Control Register 1
(Address 00H - Read/Write).
Frequency Select 1 (Input). This input, in conjunction with FS2, selects which of four
possible frequencies (8kHz, 1.544MHz, 2.048MHz or 19.44MHz) may be input to the PRI
and SEC inputs. For more details see FS1 bit description in Table 6 - Control Register 1
(Address 00H - Read/Write).
Primary Reference Out Of Range (CMOS Output). A logic high at this pin indicates that
the primary reference is off the PLL center frequency by more than 12 ppm. The
measurement is done on a 1 second basis using a signal derived from the 20MHz clock
input on C20i. When the accuracy of the 20MHz clock is
range limits of the PRIOOR signal will be 16.6ppm to -7.4ppm or +7.4ppm to -16.6ppm.
Clock 1.544MHz (CMOS Output). This output is used in T1 applications.
Clock 6.312MHz (CMOS Output). This output is used for DS2 or J2 applications.
Internal Connection. Tie low for normal operation.
Digital ground. 0 Volts
Clock 19.44MHz (CMOS Output). This output is used in OC-N and STM-N applications.
Zarlink Semiconductor Inc.
MT90401
This is one of two (PRI & SEC) input reference sources
4
This is one of two (PRI & SEC) input reference sources
Description
4.6ppm, the effective out of
Data Sheet