MT90401 Zarlink Semiconductor, MT90401 Datasheet - Page 3

• Manufacturer Part Number: MT90401
• Description: Sonet/sdh System Synchronizer
• Manufacturer: Zarlink Semiconductor

Pin Description
Pin #
7, 8
2-5
10
11
12
13
14
15
16
17
18
19
20
21
22
1
6
9
E3DS3/OC3 E3DS3 or OC-3 Selection (Input). In Hardware Mode a low on this pin enables the
SONET/SD
E3/DS3
A1 - A4
A5, A6
Name
C16o
V
F16o
V
V
MS1
MS2
C8o
C4o
C2o
F0o
F8o
IC
SS9
DD1
SS1
H
Internal Connection. Leave unconnected.
Address 1 to 4 (5V tolerant Inputs). Address inputs for the parallel processor interface.
Digital ground. 0 Volts
Address 5, to 6 (5V tolerant Input). Address inputs for the parallel processor interface.
SONET/SDH (Input). In hardware mode set this pin high to have a loop filter corner
frequency of 70 millihertz and limit the phase slope to 885 ns per second. Set this pin low to
have a corner frequency of approximately 1.1 hertz and limit the phase slope to 53 ns per
1.326 ms. This pin performs no function if the device is not in hardware mode.
Positive Power Supply. Digital supply.
Digital ground. 0 Volts
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8kHz 61ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 8.192 Mb/s.
Clock 16.384MHz (CMOS Output). This output is used for ST-BUS operation with a
16.384MHz clock.
Clock 8.192MHz (CMOS Output). This output is used for ST-BUS operation at 8.192Mb/s.
Clock 4.096MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s
and 4.096Mb/s.
Clock 2.048MHz (CMOS Output). This output is used for ST-BUS operation at 2.048Mb/s.
Frame Pulse ST-BUS 2.048Mb/s (CMOS Output). This is an 8kHz 244ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 2.048Mb/s and 4.096Mb/s.
Mode/Control Select 1 (Input). This input, together with MS2, determines the state
(Normal, Holdover, or Freerun) of operation. See Table 3 on page 15. The logic level at this
input is gated in by the rising edge of F8o. This pin performs no function if the device is not
in hardware mode.
Mode/Control Select 2 (Input). This input, together with MS1, determines the state
(Normal, Holdover or Freerun) of operation. See Table 3 on page 15. The logic level at this
input is gated in by the rising edge of F8o. This pin performs no function if the device is not
in hardware mode.
Frame Pulse Generic (CMOS Output). This is an 8kHz 122ns active high framing pulse,
which marks the beginning of a TDM frame. This is typically used for TDM streams
operating at 8.192 Mb/s.
differential 155.52MHz output clock on the C155N/C155P pins; this will also cause the
C34/C44 pin to output its nominal clock frequency divided by 4. In Hardware Mode, a high
on this pin disables the differential 155.52MHz output clock on the C155N/C155P pins; this
will also cause the C34/C44 pin to output its nominal clock frequency. This pin performs no
function if the device is not in Hardware Mode.
E3 or DS3 Selection (Input). In Hardware Mode a low on this pin selects a clock rate of
44.736MHz for the C34/C44 pin, while a high selects a clock rate of 34.368MHz. This pin
performs no function if the device is not in hardware mode.
Zarlink Semiconductor Inc.
MT90401
3
Description
Data Sheet