MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 39

• Manufacturer Part Number: MT92210
• Description: 1023 Channel Voice Over ip (VoIP) Processor
• Manufacturer: Zarlink Semiconductor

Data Sheet
5.0
This chapter describes the data flows for all packets received and transmitted.
5.1
This section resumes the typical propagation of voice data throughout the MT92210 in the receive direction, from
the link to the H.110 bus.
Packets arriving off the link are written into memories, either a cell input FIFO if the link is configured as a UTOPIA
interface, or a packet input FIFO if the link is configured as an Ethernet or Packet over SONET interface. For the
ports that are configured as UTOPIA, the cells then go through the UTOPIA look-up process, which indicates what
their nature is, either raw cells going to a cell destination, or AAL5 cells to be reassembled into a packet. After they
are looked-up, they are written into the RX link A or RX link B cell FIFO.
If port A is configured as Ethernet or POS, its packets go through a packet to block conversion process, where they
are broken down into 48-byte blocks. In addition, Ethernet headers are converted to LANEv1 headers, and POS is
mapped as PPP over AAL5. The packets are then written into the RX link A cell FIFO. As of this point, all packets
look identical within the chip, independently of the link interface.
The cells are then read by the packet reassembly process and written into external SDRAM until the packet to
which they belong is complete. Cells that are tagged as non-AAL5 pass by the packet reassembly process but are
routed immediately to their own destination, which is already known because it was indicated in the UTOPIA
look-up table. These cells may be sent back onto one of the TX links, or they may be routed directly to the CPU.
RX/TX Data Flows
RX Data Flow
Zarlink Semiconductor Inc.
MT92210
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