MT92210 Zarlink Semiconductor, MT92210 Datasheet - Page 42

• Manufacturer Part Number: MT92210
• Description: 1023 Channel Voice Over ip (VoIP) Processor
• Manufacturer: Zarlink Semiconductor

42
performed on the packet and that no HDLC address or control byte insertion will be done, it is otherwise identical to
the RX HDLC Channel Structure.
Once the bytes have been copied into the correct circular buffers, only the RX TDM process remains. The RX TDM
process is not event-driven with regards to the other processes: by following the Data Flow, we see that, from the
Packet Reassembly Process, each process has been triggered by the previous one completing and handing it over
the packet. The RX TDM only communicates with the Packet Disassembly process through the TDM pointer.
The RX TDM process reads bytes out of the PCM and HDLC circular buffers and places them onto the H.110 bus.
Each frame it reads one byte out of each xxPCM circular buffer and places it on the appropriate TSST; it uses a
channel association memory to make this connection. It also compensates for underruns and packet losses by
inserting SSRAM Tone Buffers, SDRAM Silence Buffers or Padding Octets. In HDLC, when there is no data to be
sent on a stream, it sends the idle code.
Circular Buffer
Circular Buffer
(1 per Stream)
Circular Buffer
(1 per Buffer)
(1 per Bearer)
RXCIRC2-3
RX xxPCM
RX HDLC
RXCIRC5
RXCIRC4
RX CPU
Control Table (1
RX CPU Buffer
Stream/Buffer
(1 per Stream)
Control Table
per Buffer)
RX HDLC
RXCIRC0
RXCIRC1
Extended PDV
Structure (0-1
Absorption
Monitoring
Structure)
per PDV
DISAS4
Note: The Packet Disassembly
process has interactions with all the
structures on this page. The arrows
have not all been drawn for clarity.
Packet Disassembly Process:
Performs dejittering on xxPCM data,
copies payload into circular buffer,
performs policing on HDLC & CPU
channels, reports errors & events in
the Event Report Queue.
Zarlink Semiconductor Inc.
RTP-only structures
Figure 18 - Rx Flow 3
Channel Structure
PDV Absorption
Structure (1 per
Structure (1 per
RX RTP HDLC
RTP Common
(1 per channel)
N channels)
RX RTP CPU
DISAS10
DISAS9
DISAS11
Channel
channel)
(global) RXTDM3
Disassembly
Lookup Table
Conversion
CN Packet
channel) DISAS5
RX RTP xxPCM
Process
Structure (1 per
Packet
Channel
Clock Recovery
Event Queue (2
of them, global)
CLKRECOV0-2
connection) PTM1
Type/Marker Bit
Structure (1 per
Table (1 per
Payload
Connection
connection)
RX RTP
DISAS8
Disassembly
Control FIFO
Packet
(global)
Disassembly Data
Queue (global)
RXQUEUE0-4
Event Report
FIFO (global)
Packet