MT92220BG Zarlink Semiconductor, MT92220BG Datasheet - Page 161

• Manufacturer Part Number: MT92220BG
• Description: Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608
• Manufacturer: Zarlink Semiconductor

Data Sheet
12.0
The MT92220 has 2 main clock domains: mem_clk_net and mem_clk_sar . They are used for the Network
Interface and the SAR portion of the device accordingly. These clocks can be sourced externally or created
internally using PLLs.
12.1
The clock multiplication PLLs in the MT92220 are used to take a low frequency upclk , always provided on the
upclk pin, and multiply it up to the fast_clk frequency. There, it is divided down to the mem_clk_xxx frequency.
The X, Y and Z divider can be programmed to any legal value through registers 164h or 166h (as defined in the
tables below). upclk can be fed into the device with a frequency ranging from 25 MHz to 66 MHz. Only frequencies
between 50 MHz and 53.3 MHz are not supported by the PLL. The X and Y divisor tables indicate what values to
program in the X,Y and Z registers depending on the input value of upclk . The Z divisor table indicates the range of
mem_clk_xxx that can be achieved with typical values of Z. Note that mem_clk_xxx cannot be programmed
above 100 MHz or below 40 MHz. fast_clk is used by the TDM interface and must operate between 160 MHz to
200 MHz.
The mem_clk_xxx PLL drives the output mem_clk_xxx pins. These pins provide both TTL and PECL interfaces
for mem_clk_xxx input and output. For both types, the output pins for mem_clk_xxx is always driven. However,
when the output pins are not being used, the register bits that control the toggling of these 2 pins should be
disabled to reduce power consumption.
The user must configure the MT92220 to select the desired mem_clk_xxx input type, either PECL or TTL.
mem_clk_xxx serves as the main clock for the chip and therefore must be present for the MT92220 to function. It
is absolutely necessary for mem_clk_xxx to be present and one of the inputs to be selected. The mem_clk_xxx
outputs however, are simply a convenience for the user and do not require to be connected. These outputs
eliminate the need for a second, high-speed oscillator. The user need only generate upclk .
The clock that is connected to the mem_clk_xxx inputs on the MT92220, whether it is TTL or PECL, must be in
phase with the clock connected to SSRAM used with the chip. The maximum skew allowed is ± 0.5 ns.
Clocking
Programming the mem_clk_xxx PLL
-
1
1
2
-
2
Div X
-
6
5
8
-
6
Div Y
Table 67 - Clock Divisor X and Y
Zarlink Semiconductor Inc.
0 to 30
30 to 33.33
33.33 to 40
40 to 50
50 to 53.33
53.33 to 66.66
upclk (MHz)
-
160 to 200
166.66 to 200
160 to 200
-
160 to 200
fast_clk (MHz)
MT92220
161
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