MT92220BG Zarlink Semiconductor, MT92220BG Datasheet - Page 47

• Manufacturer Part Number: MT92220BG
• Description: Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608
• Manufacturer: Zarlink Semiconductor

Data Sheet
Raw cells written into one of the TX Link Raw Cell Buffers will be transmitted onto the appropriate TX link port. Raw
cells can be transmitted onto any port configured as ATM UTOPIA. Either the TX Link A or TX Link B Copy Process
will read the cell from the Raw Cell Buffer and copy it into either the TX Link A Packet/Cell FIFO (for port A) or the
TX Link B Cell FIFO (for port B), from where it will be transmitted onto the link.
Packets written into one of the TX Link Packet Buffers will also be read out by the corresponding TX Link Copy
Process: if port A is configured as Ethernet or Packet over SONET, then the data will be written into the TX Link A
Cell FIFO. From there, the Block to Packet Conversion process will write the packet as a contiguous packet into the
TX Link A Cell/Packet FIFO, from where it will be transmitted onto the link. If port A is configured as ATM, however,
packets will get the same treatment as raw cells: written directly into the TX Link A Packet/Cell FIFO, then to the
link. Packets on port B also go through the same treatment as raw cells: they are copied into the TX Link B Cell
FIFO and transmitted onto the link.
TX AAL2 VC process: Takes AAL2 mini-packets from the Packet Assembly Control &
Data FIFOs and concatenates them into AAL2 cells.
Assembly Copying process: Copies RTP packets from the Packet Assembly Control &
Data FIFOs and writes them into SDRAM C; also writes their handles in SSRAM C.
CPU cell injection: Software process that writes cells in external SSRAM C then sends
its pointer to the correct destination.
CPU packet injection: Software process that writes packets
into blocks in external SDRAM C, then sends its handle to
the correct destination.
Packet Assembly
Packet Assembly
Control FIFO
Data FIFO
(global)
(global)
TX AAL2 VC
Structure (1
AAL2STR0
per VC)
TX AAL2 VC
Process
Assembly
Copying
Process
Zarlink Semiconductor Inc.
Figure 22 - Tx Flow 3
Network CPU Packet
CPU network
Pointers (global)
Buffer Handles
CPU cell
injection
RX CPU Raw
injection
(global) NET6
RAWCELL2)
packet
Cell Buffer
TX link A HP Packet
TX link B HP Packet
TX link A LP Packet
TX link B LP Packet
(global) RAWCELL2
(global) RAWCELL2
(global) RAWCELL2
(global) RAWCELL2
(global) RAWCELL2
(global) RAWCELL2
Buffer Handles
Buffer Handles
Buffer Handles
Buffer Handles
TX link A Raw Cell
TX link A Raw Cell
TX link A Raw Cell
TX link A Raw Cell
TX link B Raw Cell
TX link B Raw Cell
Buffer 0 Pointers
Buffer 1 Pointers
Buffer 2 Pointers
Buffer 3 Pointers
Buffer 0 Pointers
Buffer 1 Pointers
(global) NET6
(global) NET6
(global) NET6
(global) NET6
MT92220
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