MT92220BG Zarlink Semiconductor, MT92220BG Datasheet - Page 205

• Manufacturer Part Number: MT92220BG
• Description: Description = 1023 Channel Voice Over IP/AAL2 Processor ;; Package Type = Epbga ;; No. Of Pins = 608
• Manufacturer: Zarlink Semiconductor

Data Sheet
Appendix A
Notes
1. The RX Ethernet / RX POS module (eptoatm) does not pad any packets to the end of a cell. Thus a single
2. All four memory-controllers cannot limit the throughput of watomic accesses to their respective memories.
3. The number of bearers that is programmable in the disassembly structure has a maximum value of 255 rather
4. When the external SDRAM is configured to be 16 Megabytes rather than 32 Megabytes, the auto-clear function
5. The SDRAM refresh process will be active during the init of the chip. Therefore, to ensure that the SDRAM init
6. The packet disassembly module’s extended PDV monitoring section analyzes the delay of packets in the nega-
dword of random data may reside in parts of a packet that would otherwise have contained zero padding. This
abnormality has no adverse side-effects.
Thus, the software may be able to “sink” the external memory bandwidth and make the chip fail. To avoid this,
any burst of more than 16 consecutive watomic accesses should be isolated from other watomic accesses via
3 other (non-watomic) accesses. These can be three writes to registers (on the proper clock domain). So to
break up watomic accesses to memory bank A/B, writes to the mainreg can be performed; to break up watomic
accesses to memory bank C, writes to the netreg can be performed.
than 256.
will initialize the links to values in the range 16-32 Megabytes.
sequence is executed without any refresh instructions being inserted, the sdram_refresh_cnt must be
changed from a small value (e.g. 0x100) to 0xFFFF. This will create 65000 mclk_net cycles during which no
refresh instructions will be executed. Once the init sequence is complete, the sdram_refresh_cnt must be
returned to its valid value. A precise timer must be used to ensure that the sequence was executed within the
time budget.
tive direction instead of the positive direction, which means that a “late” packet will obtain a very small delta,
while an “early” packet will obtain a very large delta. Because of this, the exponential section of the delay
entries is located in the delay section in which early packet will arrive. In addition, the time_zero_delta field
must be programmed to the total number of frames of latency with which the latest packet can be expected to
arrive (from source to destination).
Zarlink Semiconductor Inc.
MT92220
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