PIC16C926-I/CL Microchip Technology, PIC16C926-I/CL Datasheet - Page 175

• Manufacturer Part Number: PIC16C926-I/CL
• Description: 64/68-Pin CMOS Microcontrollers with LCD Driver
• Manufacturer: Microchip Technology

RESET ....................................................................... 97, 101
Resistor Ladder (LCD) ....................................................... 95
RP1:RP0 (Bank Select) bits ......................................... 12, 19
S
SCL ........................................................................ 70, 71, 72
SDA .............................................................................. 71, 72
Slave Mode
SLEEP ....................................................................... 97, 101
Software Simulator (MPLAB SIM) .................................... 134
Special Features of the CPU ............................................. 97
Special Function Registers, Summary ............................... 15
SPI
SSP
SSP I
SSPEN (Sync Serial Port Enable) bit ................................. 60
SSPM3:SSPM0 .................................................................. 60
SSPOV (Receive Overflow Indicator) bit ........................... 60
SSPOV bit .......................................................................... 70
Stack .................................................................................. 25
STATUS Register .............................................................. 19
Synchronous Serial Port Mode Select bits,
2001 Microchip Technology Inc.
T1CON (Timer1 Control) ............................................ 47
T2CON (Timer2 Control) ............................................ 52
Block Diagram .......................................................... 101
RESET Conditions for PCON Register .................... 103
RESET Conditions for Program Counter ................. 103
RESET Conditions for STATUS Register ................ 103
SCL pin ...................................................................... 70
SDA pin ...................................................................... 70
Associated Registers ................................................. 64
Master Mode .............................................................. 62
Serial Clock ................................................................ 61
Serial Data In ............................................................. 61
Serial Data Out .......................................................... 61
Serial Peripheral Interface (SPI) ................................ 59
Slave Select ............................................................... 61
SPI Clock ................................................................... 62
SPI Mode ................................................................... 61
Block Diagrams
Register Initialization States ............................. 104, 105
SSPADD Register ................................................ 69, 70
SSPBUF Register .................................... 62, 69, 70, 71
SSPCON Register ............................................... 60, 69
SSPIF bit ........................................................ 70, 71, 72
SSPOV bit .................................................................. 70
SSPSR ....................................................................... 62
SSPSR Register .................................................. 70, 71
SSPSTAT ................................................................... 71
SSPSTAT Register ........................................ 59, 69, 71
Addressing ................................................................. 70
Associated Registers ................................................. 72
Multi-Master Mode ..................................................... 72
Reception ................................................................... 71
SSP I
START ....................................................................... 71
START (S) ................................................................. 72
STOP (P) ................................................................... 72
Transmission .............................................................. 71
Overflows ................................................................... 25
Underflow ................................................................... 25
Initialization States ................................................... 104
SSPM3:SSPM0 .......................................................... 60
2
C
I
SPI Mode ........................................................... 61
2
2
C Mode ............................................................ 69
C Operation ..................................................... 69
Preliminary
T
T
Timer0
Timer1
Timer2
Timing Diagrams (Operational)
AD
Associated Registers ................................................. 45
Block Diagram ........................................................... 41
Clock Source Edge Select (T0SE Bit) ....................... 20
Clock Source Select (T0CS Bit) ................................ 20
External Clock ........................................................... 43
Increment Delay ........................................................ 43
Initialization States ................................................... 104
Interrupt ..................................................................... 41
Interrupt Timing ......................................................... 42
Prescaler ................................................................... 44
Timing ........................................................................ 42
TMR0 Interrupt ........................................................ 108
Associated Registers ................................................. 50
Asynchronous Counter Mode .................................... 49
Block Diagram ........................................................... 48
Capacitor Selection ................................................... 50
External Clock Input
Oscillator .................................................................... 50
Prescaler ................................................................... 50
Reading a Free-running Timer .................................. 49
Register Initialization States .................................... 104
Resetting Register Pair .............................................. 50
Resetting with a CCP Trigger Output ........................ 50
Switching Prescaler Assignment ............................... 45
Synchronized Counter Mode ..................................... 48
T1CON Register ........................................................ 47
Timer Mode ............................................................... 48
Block Diagram ........................................................... 51
Output ........................................................................ 51
Register Initialization States .................................... 104
T2CON Register ........................................................ 52
Clock/Instruction Cycle ................................................ 9
I
I
I
I
I
I
I
INT Pin Interrupt Timing .......................................... 108
LCD Half-Duty Cycle Drive ........................................ 86
LCD Interrupt Timing in Quarter-Duty Cycle Drive .... 91
LCD One-Third Duty Cycle Drive .............................. 87
LCD Quarter-Duty Cycle Drive .................................. 88
LCD SLEEP Entry/Exit (SLPEN=1) ........................... 93
LCD Static Drive ........................................................ 85
SPI (Master Mode) .................................................... 63
SPI (Slave Mode, CKE = 0) ....................................... 63
SPI (Slave Mode, CKE = 1) ....................................... 64
Successive I/O Operation .......................................... 39
Time-out Sequences on Power-up .......................... 106
Timer0 Interrupt Timing ............................................. 42
Timer0 with External Clock ........................................ 43
.................................................................................... 79
2
2
2
2
2
2
2
C Clock Synchronization ......................................... 68
C Data Transfer Wait State ..................................... 66
C Multi-Master Arbitration ....................................... 68
C Reception (7-bit address) .................................... 71
C Slave-Receiver Acknowledge .............................. 66
C STARTand STOP Conditions .............................. 65
C Transmission (7-bit address) ............................... 71
Synchronization ................................................. 43
Timing ................................................................ 43
Block Diagram ................................................... 44
Synchronized Counter Mode ............................. 48
Timing with Unsynchronized Clock .................... 49
Unsynchronized Clock Timing ........................... 49
PIC16C925/926
DS39544A-page 173