PIC16C926-I/CL Microchip Technology, PIC16C926-I/CL Datasheet - Page 58
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PIC16C926-I/CL
Manufacturer Part Number
PIC16C926-I/CL
Description
64/68-Pin CMOS Microcontrollers with LCD Driver
Manufacturer
Microchip Technology
Datasheet
1.PIC16C926-ICL.pdf
(182 pages)
- Current page: 58 of 182
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PIC16C925/926
8.3
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTC data latch,
the TRISC<2> bit must be cleared to make the CCP1
pin an output.
Figure 8-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see Section 8.3.3.
FIGURE 8-3:
A PWM output (Figure 8-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 8-4:
DS39544A-page 56
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
Note:
CCPR1H (Slave)
Duty Cycle Registers
Comparator
CCPR1L
TMR2
PR2
TMR2 = PR2
Comparator
or 2 bits of the prescaler to create 10-bit time-base.
PWM Mode
Duty Cycle
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTC I/O data
latch.
Period
(Note 1)
Clear Timer,
CCP1 pin and
latch D.C.
TMR2 = Duty Cycle
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM OUTPUT
TMR2 = PR2
CCP1CON<5:4>
R
S
Q
TRISC<2>
RC2/CCP1
Preliminary
8.3.1
The PWM period is specified by writing to the PR2 reg-
ister. The PWM period can be calculated using the fol-
lowing formula:
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
• The PWM duty cycle is latched from CCPR1L into
8.3.2
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available; the CCPR1L contains
the eight MSbs and CCP1CON<5:4> contains the two
LSbs.
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
When the CCPR1H and 2-bit latch match TMR2, con-
catenated with an internal 2-bit Q clock, or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
cycle = 0%, the CCP1 pin will not be set)
CCPR1H
Note:
Note:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
PWM period = [ (PR2) + 1 ] • 4 • T
PWM Resolution (max)
This
The Timer2 postscaler (Section 7.0) is not
used in the determination of the PWM fre-
quency. The postscaler could be used to
have a servo update rate at a different fre-
quency than the PWM output.
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
PWM PERIOD
PWM DUTY CYCLE
10-bit
(TMR2 prescale value)
T
OSC
value
• (TMR2 prescale value)
2001 Microchip Technology Inc.
=
log
-----------------------------bits
is
log
---------------
F
F
OSC
PWM
OSC
2
represented
•
by
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