PIC18F6620 Microchip, PIC18F6620 Datasheet - Page 269

• Manufacturer Part Number: PIC18F6620
• Description: Microcontroller
• Manufacturer: Microchip

ANDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2004 Microchip Technology Inc.
Q Cycle Activity:
Before Instruction
After Instruction
Decode
W
REG
W
REG
Q1
PIC18F6520/8520/6620/8620/6720/8720
=
=
=
=
register ‘f’
AND W with f
[ label ] ANDWF
0
d
a
(W) .AND. (f)
N, Z
The contents of W are AND’ed with
register ‘f’. If ‘d’ is ‘0’, the result is
stored in W. If ‘d’ is ‘1’, the result is
stored back in register ‘f’ (default).
If ‘a’ is ‘0’, the Access Bank will be
selected. If ‘a’ is ‘1’, the BSR will
not be overridden (default).
1
1
ANDWF
Read
0001
Q2
0x17
0xC2
0x02
0xC2
f
[0,1]
[0,1]
255
01da
REG, 0, 0
Process
Data
Q3
dest
ffff
f [,d [,a]
destination
Write to
Q4
ffff
BC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
No
PC
If Carry
If Carry
Q1
Q1
PC
PC
Read literal
Read literal
operation
Branch if Carry
[ label ] BC
-128
if Carry bit is ‘1’
None
If the Carry bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
1
1(2)
HERE
(PC) + 2 + 2n
1110
No
Q2
Q2
‘n’
‘n’
=
=
=
=
=
n
address (HERE)
1;
address (HERE+12)
0;
address (HERE+2)
127
0010
operation
BC
Process
Process
Data
Data
n
No
Q3
Q3
DS39609B-page 267
5
PC
nnnn
Write to PC
operation
operation
No
No
Q4
Q4
nnnn