PIC18F6620 Microchip, PIC18F6620 Datasheet - Page 94

• Manufacturer Part Number: PIC18F6620
• Description: Microcontroller
• Manufacturer: Microchip

PIC18F6520/8520/6620/8620/6720/8720
9.2
The PIR registers contain the individual flag bits for the
peripheral interrupts. Due to the number of peripheral
interrupt sources, there are three Peripheral Interrupt
Flag Registers (PIR1, PIR2 and PIR3).
REGISTER 9-4:
DS39609B-page 92
PIR Registers
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1
PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit
1 = A read or a write operation has taken place (must be cleared in software)
0 = No read or write has occurred
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed (must be cleared in software)
0 = The A/D conversion is not complete
RC1IF: USART1 Receive Interrupt Flag bit
1 = The USART1 receive buffer, RCREG, is full (cleared when RCREG is read)
0 = The USART1 receive buffer is empty
TX1IF: USART Transmit Interrupt Flag bit
1 = The USART1 transmit buffer, TXREG, is empty (cleared when TXREG is written)
0 = The USART1 transmit buffer is full
SSPIF: Master Synchronous Serial Port Interrupt Flag bit
1 = The transmission/reception is complete (must be cleared in software)
0 = Waiting to transmit/receive
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode.
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
bit 7
Legend:
R = Readable bit
- n = Value at POR
PSPIF
R/W-0
Note 1: Enabled only in Microcontroller mode for PIC18F8X20 devices.
(1)
R/W-0
ADIF
RC1IF
R-0
W = Writable bit
‘1’ = Bit is set
TX1IF
R-0
Note 1: Interrupt flag bits are set when an interrupt
2: User software should ensure the appropri-
SSPIF
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>).
ate interrupt flag bits are cleared prior to
enabling an interrupt and after servicing
that interrupt.
(1)
CCP1IF
R/W-0
 2004 Microchip Technology Inc.
TMR2IF
R/W-0
x = Bit is unknown
TMR1IF
R/W-0
bit 0