XC2VPX70 Xilinx, XC2VPX70 Datasheet - Page 40

• Manufacturer Part Number: XC2VPX70
• Description: (XC2VPxxx) Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: Xilinx

Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Continued)
DS123 (v2.9) May 09, 2006
CEO
EN_EXT_SEL
REV_SEL0
REV_SEL1
BUSY
CLKOUT
TMS
TCK
TDI
TDO
VCCINT
Pin Name
R
Scan Order
Boundary
06
05
31
30
29
12
08
07
Output Enable
Output Enable
Mode Select
Boundary
Function
Data Out
Data Out
Data Out
Data In
Data In
Data In
Data In
Data In
Scan
Clock
Chip Enable Output. Chip Enable Output (CEO) is connected
to the CE input of the next PROM in the chain. This output is
Low when CE is Low and OE/RESET input is High, AND the
internal address counter has been incremented beyond its
Terminal Count (TC) value. CEO returns to High when
OE/RESET goes Low or CE goes High.
Enable External Selection Input. When this pin is Low, design
revision selection is controlled by the Revision Select pins.
When this pin is High, design revision selection is controlled
by the internal programmable Revision Select control bits.
EN_EXT_SEL has an internal 50KΩ resistive pull-up to V
to provide a logic 1 to the device if the pin is not driven.
Revision Select[1:0] Inputs. When the EN_EXT_SEL is Low,
the Revision Select pins are used to select the design
revision to be enabled, overriding the internal programmable
Revision Select control bits. The Revision Select[1:0] inputs
have an internal 50 KΩ resistive pull-up to V
logic 1 to the device if the pins are not driven.
Busy Input. The BUSY input is enabled when parallel mode
is selected for configuration. When BUSY is High, the internal
address counter stops incrementing and the current data
remains on the data pins. On the first rising edge of CLK after
BUSY transitions from High to Low, the data for the next
address is driven on the data pins. When serial mode or
decompression is enabled during device programming, the
BUSY input is disabled. BUSY has an internal 50 KΩ
resistive pull-down to GND to provide a logic 0 to the device
if the pin is not driven.
Configuration Clock Output. An internal Programmable
control bit enables the CLKOUT signal, which is sourced from
either the internal oscillator or the CLK input pin. Each rising
edge of the selected clock source increments the internal
address counter if data is available, CE is Low, and
OE/RESET is High. Output data is available on the rising
edge of CLKOUT. CLKOUT is disabled if CE is High or
OE/RESET is Low. If decompression is enabled, CLKOUT is
parked High when decompressed data is not ready. When
CLKOUT is disabled, the CLKOUT pin is put into a high-Z
state. If CLKOUT is used, then it must be pulled High
externally using a 4.7 KΩ pull-up to V
JTAG Mode Select Input. The state of TMS on the rising edge
of TCK determines the state transitions at the Test Access
Port (TAP) controller. TMS has an internal 50 KΩ resistive
pull-up to V
not driven.
JTAG Clock Input. This pin is the JTAG test clock. It
sequences the TAP controller and all the JTAG test and
programming electronics.
JTAG Serial Data Input. This pin is the serial input to all JTAG
instruction and data registers. TDI has an internal 50 KΩ
resistive pull-up to V
the pin is not driven.
JTAG Serial Data Output. This pin is the serial output for all
JTAG instruction and data registers. TDO has an internal
50KΩ resistive pull-up to V
system if the pin is not driven.
+1.8V Supply. Positive 1.8V supply voltage for internal logic.
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Platform Flash In-System Programmable Configuration PROMS
CCJ
to provide a logic 1 to the device if the pin is
CCJ
Pin Description
to provide a logic 1 to the device if
CCJ
to provide a logic 1 to the
CCO
.
CCO
to provide a
CCO
4, 15, 34
VOG48)
(VO48/
48-pin
TSOP
10
25
26
27
21
20
19
22
5
9
TFBGA
FSG48)
B1, E1,
48-pin
(FS48/
G3
G4
G1
G6
D2
H4
C1
C2
E2
H3
E6
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