XC2VPX70 Xilinx, XC2VPX70 Datasheet - Page 41

• Manufacturer Part Number: XC2VPX70
• Description: (XC2VPxxx) Platform Flash In-System Programmable Configuration PROMS
• Manufacturer: Xilinx

Table 14: XCFxxP Pin Names and Descriptions (VO48/VOG48 and FS48/FSG48) (Continued)
XCFxxP VO48/VOG48 Pinout Diagram
DS123 (v2.9) May 09, 2006
VCCO
VCCJ
GND
DNC
Pin Name
OE/RESET
CLKOUT
VCCINT
VCCINT
R
VCCO
BUSY
VCCJ
DNC
GND
DNC
GND
CEO
DNC
DNC
GND
DNC
GND
TMS
TDO
TCK
CLK
TDI
CE
CF
Scan Order
Boundary
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Figure 16: VO48/VOG48 Pinout Diagram (Top View) with Pin Names
Boundary
Function
Scan
+3.3V, 2.5V, or 1.8V I/O Supply. Positive 3.3V, 2.5V, or 1.8V
supply voltage connected to the output voltage drivers and
input buffers.
+3.3V or 2.5V JTAG I/O Supply. Positive 3.3V, 2.5V, or 1.8V
supply voltage connected to the TDO output voltage driver
and TCK, TMS, and TDI input buffers.
Ground
Do Not Connect. (These pins must be left unconnected.)
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Platform Flash In-System Programmable Configuration PROMS
VO48/VOG48
View
Top
Pin Description
ds123_24_070505
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
18, 35, 37,
39, 40, 41,
31, 36, 46
VOG48)
D7
D6
GND
VCCO
D5
D4
DNC
DNC
DNC
DNC
VCCO
DNC
GND
DNC
VCCINT
D3
D2
GND
VCCO
D1
D0
REV_SEL1
REV_SEL0
EN_EXT_SEL
(VO48/
17, 23,
14, 16,
48-pin
TSOP
38, 45
8, 30,
2, 7,
1, 3,
24
42
F5, F6, H1
TFBGA
FSG48)
C4, D3,
B2, C6,
A1, A2,
A4, C3,
D4, E3,
D6, G5
B6, F1,
E4, F2,
F3, F4,
48-pin
(FS48/
G2
H2
41