ISL6534 Intersil Corporation, ISL6534 Datasheet - Page 20

• Manufacturer Part Number: ISL6534
• Description: Dual PWM
• Manufacturer: Intersil Corporation

www.DataSheet4U.com
Note that the PHASE node is not brought into the ISL6534,
so there is no way to reference the gate voltage to it, as is
often done in other regulators. The considerations for the
BOOT2 pin are identical to BOOT1; but since they may have
different VIN, VOUT, FETs, etc., the preferred solution for
each output may be different for any given system.
The voltage required on V
diode anode) depends primarily on the upper NFET r
and Vth. A high voltage makes the r
possible, which should help the overall efficiency; however,
the high voltage makes the switching power in the gate driver
higher, which lowers the efficiency. So the net overall effect is
a trade-off between the two. At the other extreme, the
voltage must be at least as high as the FET threshold
voltage, plus a few volts of overdrive, in order to turn on the
NFET hard enough to source the maximum load current. So
the r
driver power is lower, which helps the efficiency.
Since the gate driver power is a function of (voltage)
theoretical optimum V
enough to turn on the NFET to handle the maximum load.
However, since there are usually only a few available power
supplies to choose from, the user often must compromise.
And sometimes the only supply available is the same one
used for VIN, which may be good for one term, but not as
good for the other.
The size of the bootstrap capacitor can be chosen by using
the following equations:
The last equation plugs in some typical values: N = 1; Q
33nC, VIN is 12V, V
C
as a starting value. Note that bootstrap capacitors usually
need to be rated at 16V, to handle the typical 12V boot.
Note that in general, as the number of FETs or the size of
the FETs increases (which usually makes Q
VIN or the bootstrap supply (if not VIN) increases (for
example, from 5V to 12V), these all require that C
become larger.
C
C
where
N is the number of upper FETs
Q
VIN is the input voltage
V
∆V is the change in boot voltage before and immediately
after the transfer of charge; typically 0.7V to 1.0V
BOOT
BOOT
BOOT
GS
G
DS(ON)
is the total gate charge per upper FET
is the gate-source voltage (usually VIN - diode drop)
≥
≥
≥ 0.051µF. This value is often rounded up to 0.1µF
Q
------------------- -
Q
------------------- -
GATE
GATE
∆V
∆V
is not as low, hurting the efficiency, but the gate
=
N Q
-----------------------------------
and
GS
V
•
GS
BOOT
is 11V, ∆V
G
•
•
BOOT
∆V
Q
VIN
GATE
voltage is to make it only high
20
=
(Bootstrap Voltage; the
1 33 12
--------------------------- -
max
=
11 0.7
•
DS(ON)
N Q
---------------------------------- -
•
= 1V. In this example,
•
•
V
G
GS
=
•
as low as
G
VIN
0.051µF
larger) or if
BOOT
2
DS(ON)
, the
G
is
ISL6534
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient (and usually
increases the DCR of the inductor, which decreases the
efficiency). Increasing the switching frequency (Fs) for a
given inductor also reduces the ripple current and voltage.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6534 will provide either 0% or 87.5% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
where: I
response time to the application of load, and t
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for the
worst case response time.
Output Capacitors Selection
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
∆I =
t
RISE
V
------------------------------- -
IN
=
Fs x L
TRAN
------------------------------- -
V
L
- V
O
IN
OUT
×
–
I
V
TRAN
is the transient load current step, t
OUT
•
V
--------------- -
V
OUT
IN
t
FALL
∆V
=
OUT
L
------------------------------ -
O
V
×
= ∆I x ESR
OUT
I
TRAN
FALL
RISE
is the
FN9134.1
is the