ISL6534 Intersil Corporation, ISL6534 Datasheet - Page 24

• Manufacturer Part Number: ISL6534
• Description: Dual PWM
• Manufacturer: Intersil Corporation

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Layout Considerations for the ISL6534
The metal plate on the bottom of either the TSSOP or QFN
(MLFP) package must be soldered down to the PC board,
and sufficient plane area given for heat transfer. The plane
should be connected to GND (pin 15 in TSSOP); but if it is
left floating, it should NOT be tied to any other potential.
Thermal vias are recommended to connect to a plane on the
opposite side of the PCB, and to the internal GND plane, for
additional heat transfer.
Decoupling capacitors should be very close to the VCC12
and VCC5 pins, with vias to the GND plane.
The traces from the gate drivers to the FETs (UG1, UG2,
LG1, LG2, DRIVE3) should be short (for low resistance) and
wide (to handle large currents); the pin spacing will limit the
widths right near the package. But note that the closer the
FETs are to the IC, the more they will heat each other, so
keep that thermal consideration in mind.
BOOT1/2 capacitors should be near their pins; the bottom to
phase and diode can be a little further away. If a separate
small capacitor is used for the bootstrap supply (if different
than either VIN or VCC12), it should be located next to the
bootstrap diode anode.
C
FIGURE 22. PRINTED CIRCUIT BOARD SMALL SIGNAL
VCC
C
SS
GND
SS
VCC
GND
ISL6534
LAYOUT GUIDELINES
VCC12
PGND
BOOT
C
BOOT
+12V
PHASE
24
C
VCC12
D1
Q1
+V
Q2
IN
L
O
C
O
V
OUT
ISL6534
Other traces to keep short include:
• FB1/2/3: the resistor dividers should be near the IC; via to
• Resistor dividers used for references (from VREF or
• COMP1/2: the compensation components should be close
• EN_SS capacitors should be near pin, with vias to GND
• FS_SYNC resistor (if needed) should be near pin, with a
• Output capacitors should be close to the loads, where the
• The VIN plane should be large to heatsink the upper FET
Several placement approaches are possible:
• IC and output FETs, caps, and inductors on top level; most
• All components on top level, with output components
GND plane; the signal from the VOUT can travel, since it is
low impedance.
VOUT or to REFIN) should be near the REFIN input.
to these pins (as well as FB1/2 pins), with vias to the GND
plane.
plane.
via to GND.
filtering will help most; small ceramic capacitors (~1µF) in
parallel help for high frequency transients. Input capacitors
should be near the VIN pins of the FETs; the input
capacitor GNDs should be close to the lower FET GND as
well.
effectively, since the drain pin is usually the thermal node.
By the same reasoning then, the phase node plane should
also be large, since the lower FET drain is connected
there. However, the phase node plane couples high
frequency switching noise to other levels nearby, so it
should be minimized for that reason. And don’t route any
sensitive or high impedance signals over the phase
planes.
of the miscellaneous resistors and capacitors on the
bottom level;
facing pins 13-24 side of IC, and input components facing
pins 1-12.
FN9134.1