ISL8105B Intersil Corporation, ISL8105B Datasheet - Page 6

• Manufacturer Part Number: ISL8105B
• Description: Single-Phase Synchronous Buck Converter PWM
• Manufacturer: Intersil Corporation

Functional Description
Initialization (POR and OCP Sampling)
Figure 1 shows a start-up waveform of ISL8105B. The
Power-On-Reset (POR) function continually monitors the
bias voltage at the VBIAS pin. Once the rising POR
threshold is exceeded 4V (V
initiates the Overcurrent Protection (OCP) sample and hold
operation (while COMP/EN is ~1V). When the sampling is
complete, V
If the COMP/EN pin is held low during power-up, the
initialization will be delayed until the COMP/EN is released
and its voltage rises above the V
Figure 2 shows a typical power-up sequence in more detail.
The initialization starts at T0, when either V
V
COMP/EN will be pulled up by an internal 20µA current
source, but the timing will not begin until the COMP/EN
exceeds the V
capacitance of the disabling device, as well as the
compensation capacitors, will determine how quickly the
20µA current source will charge the COMP/EN pin. With
POR
FIGURE 2. BGATE/BSOC AND SOFT-START OPERATION
, or the COMP/EN pin is released (after POR). The
T0
FIGURE 1. POR AND SOFT-START OPERATION
~4V POR
OUT
T1
3.4ms
DISABLE
BGATE/BSOC
begins the soft-start ramp.
COMP/EN
3.4ms
trip point (at T1). The external
T2 T3
POR
6
0ms TO 3.4ms
V
DISABLE
BGATE
STARTS
SWITCHING
T4
nominal), the POR function
OUT
trip point.
BIAS
rises above
V
V
COMP/EN
BIAS
V
OUT
T5
ISL8105B
typical values, it should add a small delay compared to the
soft-start times. The COMP/EN will continue to ramp to ~1V.
From T1, there is a nominal 6.8ms delay, which allows the
VBIAS pin to exceed 6.5V (if rising up towards 12V), so that
the internal bias regulator can turn on cleanly. At the same
time, the BGATE/BSOC pin is initialized by disabling the
BGATE driver and drawing BSOC (nominal 21.5µA) through
R
trip point. At T2, there is a variable time period for the OCP
sample and hold operation (0ms to 3.4ms nominal; the
longer time occurs with the higher overcurrent setting). The
sample and hold uses a digital counter and DAC to save the
voltage, so the stored value does not degrade, for as long as
the V
(OCP)” on page 7 for more details on the equations and
variables. Upon the completion of sample and hold at T3, the
soft-start operation is initiated, and the output voltage ramps
up between T4 and T5.
Soft-Start and Pre-Biased Outputs
Functionally, the soft-start internally ramps the reference on
the non-inverting terminal of the error amp from zero to 0.6V
in a nominal 13.6ms. The output voltage will thus follow the
ramp, from zero to final value, in the same 13.6ms (the
actual ramp seen on the V
time), due to some initialization timing, between T3 and T4).
The ramp is created digitally, so there will be 64 small
discrete steps. There is no simple way to change this ramp
rate externally.
After an initialization period (T3 to T4), the error amplifier
(COMP/EN pin) is enabled, and begins to regulate the
converter's output voltage during soft-start. The oscillator's
triangular waveform is compared to the ramping error
amplifier voltage. This generates LX pulses of increasing
width that charge the output capacitors. When the internally
generated soft-start voltage exceeds the reference voltage
(0.6V), the soft-start is complete and the output should be in
regulation at the expected voltage. This method provides a
rapid and controlled output voltage rise; there is no large
inrush current charging the output capacitors. The entire
start-up sequence from POR typically takes up to 23.8ms; up
to 10.2ms for the delay and OCP sample and 13.6ms for the
soft-start ramp.
Figure 3 shows the normal curve in yellow; initialization
begins at T0, and the output ramps between T1 and T2. If
the output is pre-biased to a voltage less than the expected
value, as shown by the green curve, the ISL8105B will
detect that condition. Neither MOSFET will turn on until the
soft-start ramp voltage exceeds the output; V
seamlessly ramping from there. If the output is pre-biased to
a voltage above the expected value, as in the red curve,
neither MOSFET will turn on until the end of the soft-start, at
which time it will pull the output voltage down to the final
value. Any resistive load connected to the output will help
BSOC
BIAS
. This sets up a voltage that will represent the BSOC
is above V
POR
. See “Overcurrent Protection
OUT
will be less than the nominal
OUT
February 13, 2007
starts
FN6447.0