ISL8105B Intersil Corporation, ISL8105B Datasheet - Page 8

• Manufacturer Part Number: ISL8105B
• Description: Single-Phase Synchronous Buck Converter PWM
• Manufacturer: Intersil Corporation

The overcurrent function will trip at a peak inductor current
(I
where I
typical). The scale factor of 2 doubles the trip point of the
MOSFET voltage drop, compared to the setting on the
R
due to the MOSFET's r
current and temperature). To avoid overcurrent tripping in
the normal operating load range, find the R
from Equation 1 with:
For an equation for the ripple current, see “Output Inductor
Selection” on page 12.
The range of allowable voltages detected
(2 * I
range for typical MOSFETs is typically in the 20mV to 120mV
I
PEAK
1. The maximum r
2. The minimum I
3. Determine I
PEAK
BSOC
temperature
ΔI
BSOC
) determined by:
=
is the output inductor ripple current.
BSOC
resistor. The OC trip point varies in a system mainly
2
----------------------------------------------------- -
FIGURE 4. BGATE PULSE STRETCHING
×
* R
I
BSOC
is the internal BSOC current source (21.5µA
BSOC
r
DS ON
PEAK
(
×
BSOC
DS(ON)
) is 0mV to 475mV; but the practical
R
)
for I
BSOC
DS(ON)
BGATE < 425ns
BGATE << 425ns
BGATE > 425ns
BGATE = 425ns
from the specification table
PEAK
BGATE > 425ns
BGATE = 425ns
BGATE < 425ns
BGATE < 425ns
at the highest junction
8
variations (over process,
> I
OUT(MAX)
BSOC
+
(
--------- -
ΔI
2
resistor
)
, where
(EQ. 1)
ISL8105B
ballpark (500Ω to 3000Ω). If the voltage drop across R
is set too low, that can cause almost continuous OCP
tripping and retry. It would also be very sensitive to system
noise and inrush current spikes, so it should be avoided. The
maximum usable setting is around 0.2V across R
(0.4V across the MOSFET); values above that might disable
the protection. Any voltage drop across R
greater than 0.3V (0.6V MOSFET trip point) will disable the
OCP. The preferred method to disable OCP is simply to
remove the resistor, which will be detected as no OCP.
Note that conditions during power-up or during a retry may
look different than normal operation. During power-up in a
12V system, the IC starts operation just above 4V; if the
supply ramp is slow, the soft-start ramp might be over well
before 12V is reached. So with bottom-side gate drive
voltages, the r
power-up, effectively lowering the OCP trip. In addition, the
ripple current will likely be different at lower input voltage.
Another factor is the digital nature of the soft-start ramp. On
each discrete voltage step, there is in effect a small load
transient, and a current spike to charge the output
capacitors. The height of the current spike is not controlled; it
is affected by the step size of the output, the value of the
output capacitors, as well as the IC error amp compensation.
So it is possible to trip the overcurrent with inrush current, in
addition to the normal load and ripple considerations.
Figure 5 shows the output response during a retry of an
output shorted to GND. At time T0, the output has been
turned off, due to sensing an overcurrent condition. There
are two internal soft-start delay cycles (T1 and T2) to allow
the MOSFETs to cool down, to keep the average power
dissipation in retry at an acceptable level. At time T2, the
output starts a normal soft-start cycle, and the output tries to
ramp. If the short is still applied, and the current reaches the
BSOC trip point any time during soft-start ramp period, the
output will shut off and return to time T0 for another delay
cycle. The retry period is thus two dummy soft-start cycles
FIGURE 5. OVERCURRENT RETRY OPERATION
V
T0
OUT
DS(ON)
2 SOFT-START CYCLES
of the MOSFETs will be higher during
T1
BSOC
T2
February 13, 2007
that is
BSOC
FN6447.0
BSOC