ISL8105B Intersil Corporation, ISL8105B Datasheet - Page 9

• Manufacturer Part Number: ISL8105B
• Description: Single-Phase Synchronous Buck Converter PWM
• Manufacturer: Intersil Corporation

plus one variable one (which depends on how long it takes to
trip the sensor each time). Figure 5 shows an example
where the output gets about half-way up before shutting
down; therefore, the retry (or hiccup) time will be around
34ms. The minimum should be nominally 27.2ms and the
maximum 40.8ms. If the short condition is finally removed,
the output should ramp up normally on the next T2 cycle.
Starting up into a shorted load looks the same as a retry into
that same shorted load. In both cases, OCP is always
enabled during soft-start; once it trips, it will go into retry
(hiccup) mode. The retry cycle will always have two dummy
time-outs, plus whatever fraction of the real soft-start time
passes before the detection and shutoff; at that point, the
logic immediately starts a new two dummy cycle time-out.
Output Voltage Selection
The output voltage can be programmed to any level between
the 0.6V internal reference, up to the V
ISL8105B can run at near 100% duty cycle at zero load, but
the r
something less as the load current increases. In addition, the
OCP (if enabled) will also limit the maximum effective duty
cycle.
An external resistor divider is used to scale the output
voltage relative to the internal reference voltage, and feed it
back to the inverting input of the error amp. See “Typical
Application Diagram” for more detail; R
resistor; R
The recommended value for R
accuracy) and then R
equation below. Since R
(see “Feedback Compensation” on page 11), it is often
easier to change R
that way the compensation calculations do not need to be
repeated. If V
Output voltages less than 0.6V are not available.
Input Voltage Considerations
The “Typical Application Diagram” shows a standard
configuration where V
(±20%); in each case, the gate drivers use the V
for BGATE and BOOT/TGATE. In addition, V
to work anywhere from 6.5V up to the 14.4V maximum. The
V
long-term reliability reasons, but transitions through it to
voltages above 6.5V are acceptable.
There is an internal 5V regulator for bias; it turns on between
5.5V and 6.5V. Some of the delay after POR is there to allow
a typical power supply to ramp up past 6.5V before the soft-
R
V
BIAS
OUT
0
=
DS(ON)
----------------------------------
V
range between 5.5V and 6.5V is NOT allowed for
=
R
OUT
0.6V
1
OFFSET
•
0.6V
–
of the top-side MOSFET will effectively limit it to
OUT
0.6V
•
(
------------------------- -
R
1
= 0.6V, then R
R
(shortened to R
OFFSET
+
0
R
OFFSET
BIAS
0
)
1
is part of the compensation circuit
is either 5V (±10%) or 12V
to change the output voltage;
9
is chosen according to the
1
is 1kΩ to 5kΩ (±1% for
OFFSET
0
below) is the lower one.
Bias
1
is the upper
can be left open.
supply. The
BIAS
BIAS
is allowed
voltage
(EQ. 2)
(EQ. 3)
ISL8105B
start ramps begins. This prevents a disturbance on the
output, due to the internal regulator turning on or off. If the
transition is slow (not a step change), the disturbance should
be minimal. So while the recommendation is to not have the
output enabled during the transition through this region, it
may be acceptable. The user should monitor the output for
their application to see if there is any problem.
The V
as V
sources, such as outputs of other regulators. If V
powers up first, and the V
initialization is done, then the soft-start will not be able to
ramp the output, and the output will later follow part of the
V
change the sequencing of the supplies, or use the
COMP/EN pin to disable V
Figure 6 shows a simple sequencer for this situation. If V
powers up first, Q
Q
on, the resistor divider R
on, which will turn off Q
powers up first, Q
will start-up as soon as V
point is 0.4V nominal, so a wide variety of NFET's or NPN's or
even some logic IC's can be used as Q
low leakage when off (open-drain or open-collector) so as not to
interfere with the COMP output. Q
the COMP/EN pin.
The V
0.6V reference). It can be as high as 20V (for V
below V
voltage.
The first consideration for high V
voltage of 36V. The V
voltage - the diode drop), + any ringing (or other transients)
on the BOOT pin must be less than 36V. If V
limits V
The second consideration for high V
- V
+ V
So based on typical circuits, a 20V maximum V
starting assumption; the user should verify the ringing in their
particular application.
IN
2
BIAS
BIAS
on, keeping the ISL8105B in shut-down. When V
ramp when it is applied. If this is not desired, then
BIAS
IN
IN
) voltage; this must be less than 24V. Since BOOT = V
BIAS
IN
+ ringing, that reduces to (V
to the top-side MOSFET can share the same supply
range can be as low as ~1V (for V
but can also run off a separate supply or other
). There are some restrictions for running high V
+ ringing to 16V.
FIGURE 6. SEQUENCER CIRCUIT
R
1
1
R
1
2
will be off, and R
will be on, turning Q
V
IN
IN
2
1
and release the shut-down. If V
BIAS
(as seen on LX) + V
R
and R
Q
V
IN
3
BIAS
OUT
1
is not present by the time the
comes up. The V
2
until both supplies are ready.
TO COMP/EN
determines when Q
2
IN
Q
should also be placed near
IN
3
2
IN
is the maximum BOOT
pulling to V
+ ringing) must be <24V.
is the maximum (BOOT
1
2
or Q
off; so the ISL8105B
OUT
2
; but Q
BIAS
IN
IN
DISABLE
BIAS
as low as the
is 20V, that
OUT
is a good
February 13, 2007
BIAS
(boot
IN
2
1
will turn
must be
just
turns
turns
FN6447.0
IN
BIAS
trip
IN
IN