IDT72V295 Integrated Device Technology, IDT72V295 Datasheet - Page 11

• Manufacturer Part Number: IDT72V295
• Description: 128k X 18 Supersync Fifo, 3.3v
• Manufacturer: Integrated Device Technology

Retransmit setup by setting OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
If FWFT mode is selected, the FIFO will mark the beginning of the
When OR goes LOW, Retransmit setup is complete; at the same time,
TM
131,072 x 18, 262,144 x 18
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and PAF flags begin with the rising edge of RCLK that RT is setup. PAE is
synchronized to RCLK, thus on the second rising edge of RCLK after RT is
setup, the PAE flag will be updated. HF is asynchronous, thus the rising
edge of RCLK that RT is setup will update HF. PAF is synchronized to WCLK,
thus the second rising edge of WCLK that occurs t
of RCLK that RT is setup will update PAF. RT is synchronized to RCLK.
For either IDT Standard mode or FWFT mode, updating of the PAE, HF
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SKEW
after the rising edge