IDT72V295 Integrated Device Technology, IDT72V295 Datasheet - Page 9

• Manufacturer Part Number: IDT72V295
• Description: 128k X 18 Supersync Fifo, 3.3v
• Manufacturer: Integrated Device Technology

17
17
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
17
17
16
16
15
15
IDT72V295 (131,072 x 18-BIT)
EMPTY OFFSET (LSB) REGISTER
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
03FFH if LD is HIGH at Master Reset
007FH if LD is LOW at Master Reset,
FULL OFFSET (LSB) REGISTER
TM
LD
0
0
0
X
1
1
1
131,072 x 18, 262,144 x 18
DEFAULT VALUE
DEFAULT VALUE
WEN
X
0
1
1
1
0
1
REN
X
1
0
1
1
0
1
Figure 4. Programmable Flag Offset Programming Sequence
Figure 3. Offset Register Location and Default Values
SEN
1
1
1
1
X
X
X
1
0
(MSB) REGISTER
(MSB) REGISTER
EMPTY OFFSET
FULL OFFSET
DEFAULT
DEFAULT
0
0H
0H
WCLK
0
X
X
X
X
0
0
RCLK
9
X
X
X
X
X
17
17
17
17
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
34 bits for the 72V295
36 bits for the 72V2105
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Read Memory
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
No Operation
Write Memory
No Operation
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
16
16
15
15
IDT72V2105 (262,144 x 18-BIT)
IDT72V295
IDT72V2105
03FFH if LD is HIGH at Master Reset
03FFH if LD is HIGH at Master Reset
EMPTY OFFSET (LSB) REGISTER
007FH if LD is LOW at Master Reset,
007FH if LD is LOW at Master Reset,
FULL OFFSET (LSB) REGISTER
DEFAULT VALUE
DEFAULT VALUE
4668 drw 07
2 1
2 1
(MSB) REGISTER
(MSB) REGISTER
EMPTY OFFSET
FULL OFFSET
DEFAULT
DEFAULT
0H
0H
4668 drw 06
0
0
0
0