IDT72V295 Integrated Device Technology, IDT72V295 Datasheet - Page 21

• Manufacturer Part Number: IDT72V295
• Description: 128k X 18 Supersync Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D - 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
3. OE = LOW
4. W
5. There must be at least two words written to the FIFO before a Retransmit operation can be invoked.
NOTE:
1. X = 16 for the IDT72V295 and X = 17 for the IDT72V2105.
Q
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
WCLK
RCLK
0
procedure. D = 131,073 for the IDT72V295 and 262,145 for the IDT72V2105.
WEN
REN
- Q
PAE
PAF
1
OR
, W
HF
WCLK
RT
n
SEN
2
, W
LD
SI
t
ENS
3
= first, second and third words written to the FIFO after Master Reset.
W
x
TM
131,072 x 18, 262,144 x 18
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
t
ENH
t
ENS
BIT 0
t
t
t
ENS
t
LDS
RTS
DS
t
RTS
t
W
t
LDH
ENH
x+1
t
t
t
REF
ENH
HF
t
EMPTY OFFSET
SKEW2
1
Figure 12. Retransmit Timing (FWFT Mode)
2
t
PAF
1
t
A
BIT X
t
REF
21
t
(1)
ENS
W
BIT 0
1
(4)
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2
t
A
t
PAE
FULL OFFSET
W
2
(4)
3
t
A
W
3
BIT X
(4)
t
t
t
ENH
LDH
DH
(1)
4668 drw 16
4
t
A
W
4668 drw 15
4
t
ENH