IDT72V295 Integrated Device Technology, IDT72V295 Datasheet - Page 3

• Manufacturer Part Number: IDT72V295
• Description: 128k X 18 Supersync Fifo, 3.3v
• Manufacturer: Integrated Device Technology

appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and enabling
a rising RCLK edge, will shift the word from internal memory to the data
output lines.
to the data output lines after three transitions of the RCLK signal. A REN
does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on REN for access.
The state of the FWFT/SI input during Master Reset determines the timing
mode in use.
can provide, the FWFT timing mode permits depth expansion by chaining
FIFOs in series (i.e. the data outputs of one FIFO are connected to the
corresponding data inputs of the next). No external logic is required.
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and PAF (Programmable Almost-Full flag). The EF and
FF functions are selected in IDT Standard mode. The IR and OR functions
are selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespective of timing mode.
in memory. (See Table I and Table II.) Programmable offsets determine
the flag switching threshold and can be loaded by two methods: parallel or
serial. Two default offset settings are also provided, so that PAE can be set
to switch at 127 or 1,023 locations from the empty boundary and the PAF
threshold can be set at 127 or 1,023 locations from the full boundary. These
choices are made with the LD pin during Master Reset.
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
FIRST WORD FALL THROUGH/SERIAL INPUT
In IDT Standard mode, the first word written to an empty FIFO will not
In FWFT mode, the first word written to an empty FIFO is clocked directly
For applications requiring more data storage capacity than a single FIFO
PAE and PAF can be programmed independently to switch at any point
These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),
PROGRAMMABLE ALMOST-FULL (PAF)
FULL FLAG/INPUT READY (FF/IR)
TM
131,072 x 18, 262,144 x 18
Figure 1. Block Diagram of Single 131,072 x 18 and 262,144 x 18 Synchronous FIFO
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
SERIAL ENABLE(SEN)
DATA IN (D
PARTIAL RESET (PRS)
LOAD (LD)
(FWFT/SI)
0
- D
n
)
72V2105
72V295
3
IDT
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming, WEN together with LD on each rising edge of WCLK,
are used to load the offset registers via D
rising edge of RCLK can be used to read the offsets in parallel from Q
regardless of whether serial or parallel offset loading has been selected.
write pointers are set to the first location of the FIFO. The FWFT pin selects
IDT Standard mode or FWFT mode. The LD pin selects either a partial flag
default setting of 127 with parallel programming or a partial flag default
setting of 1,023 with serial programming. The flags are updated according
to the timing mode and default offsets selected.
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect. PRS is useful for resetting a device in mid-
operation, when reprogramming partial flags would be undesirable.
on the RT input during a rising RCLK edge initiates a retransmit operation
by setting the read pointer to the first location of the memory array.
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by
activating control inputs) will immediately take the device out of the power
down state.
cron CMOS technology.
MASTER RESET (MRS)
For serial programming, SEN together with LD on each rising edge of
During Master Reset (MRS) the following events occur: The read and
The Partial Reset (PRS) also sets the read and write pointers to the first
The Retransmit function allows data to be reread from the FIFO. A LOW
If, at any time, the FIFO is not actively performing an operation, the chip
The IDT72V295/72V2105 are fabricated using IDT’s high speed submi-
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
READ CLOCK (RCLK)
READ ENABLE (REN)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF FULL FLAG (HF)
DATA OUT (Q
OUTPUT ENABLE (OE)
0
- Q
n
)
n
. REN together with LD on each
4668 drw 03
n