IDT72V295 Integrated Device Technology, IDT72V295 Datasheet - Page 23

• Manufacturer Part Number: IDT72V295
• Description: 128k X 18 Supersync Fifo, 3.3v
• Manufacturer: Integrated Device Technology

NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 131,072 for the IDT72V295 and 262,144 for the IDT72V2105.
2. For FWFT mode: D = maximum FIFO depth. D = 131,073 for the IDT72V295 and 262,145 for the IDT72V2105.
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
5. PAE is asserted and updated on the rising edge of WCLK only.
WCLK
WCLK
IDT72V295/72V2105 3.3V HIGH DENSITY CMOS
SUPERSYNC FIFO
RCLK
RCLK
WEN
WEN
WCLK and the rising edge of RCLK is less than t
REN
REN
SKEW2
PAE
HF
t
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus t
CLKH
TM
t
ENS
131,072 x 18, 262,144 x 18
n words in FIFO
n+1 words in FIFO
Figure 17. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
t
CLKL
t
ENH
t
[
(2)
SKEW2
1
D -1
,
(3)
D/2 words in FIFO
2
Figure 18. Half-Full Flag Timing (IDT Standard and FWFT Modes)
SKEW2
+ 1
(4)
]
, then the PAE deassertion may be delayed one extra RCLK cycle.
words in FIFO
t
PAE
t
CLKH
2
(1)
,
(2)
t
ENS
t
CLKL
23
t
ENS
t
ENH
t
HF
n+1 words in FIFO
n+2 words in FIFO
t
ENS
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
t
[
ENH
D/2 + 1 words in FIFO
D-1
2
+ 2
(2)
(3)
]
,
words in FIFO
1
t
HF
(1)
,
(2)
t
PAE
PAE
). If the time between the rising edge of
[
2
D-1
2
D/2 words in FIFO
+ 1
n words in FIFO
n+1 words in FIFO
]
words in FIFO
4668 drw 20
4668 drw 21
(1)
,
(2)
(2)
,
(3)