MAS281 Dynex, MAS281 Datasheet - Page 12

• Manufacturer Part Number: MAS281
• Description: MIL-STD-1750A Microprocessor
• Manufacturer: Dynex

MAS281
3.2 INSTRUCTION EXECUTION
begin instruction execution. Instruction execution is
characterised by a variety of operations, each one or more
machine cycles in duration. Depending on the instruction
being executed at the time, these operations include: (1)
internal CPU cycles, (2) instruction fetches, (3) operand
transfers, and (4) input/output transfers. Instruction execution
may be interrupted at the end of any individual machine cycle
by DMA operations and at the conclusion of any given
instruction by an interrupt or Hold request.
3.2.1 INTERNAL CPU CYCLES
manipulation and housekeeping operations. Internal CPU
cycles are either five or six oscillator periods in duration and
are characterised by AS low and DSN, DDN and M/ION high.
Section 6.0 provides timing characteristics for internal CPU
cycles. Tables 7a and 7b in Section 4.0 provide machine cycle
counts (both the five and the six OSC cycle variety) associated
with each MIL-STD-1750A instruction.
3.2.2 INSTRUCTION FETCHES
pipeline full. This ensures that the next instruction is always
ready for execution when the preceding instruction is
completed. During jump and branch instruction execution, the
pipeline is flushed, and then it is refilled via two consecutive
instruction fetches starting at the new instruction location. The
pipeline is also refilled as part of interrupt and hold request
processing.
are otherwise identical to an operand read transfer. For a
detailed explanation of the function of various bus control
signals during instruction fetches, refer to the discussion of
operand transfers below. Section 6.0 provides timing
characteristics for instruction fetches. Machine cycles
associated with instruction fetches are a minimum of five
oscillator periods in duration. The RDYN signal may be used to
insert wait states to accommodate slow memory. Machine
cycle counts included in Table 7a of Section 4.0 include
instruction fetches.
IB, the instruction counter (IC), and the data input register (Dl)
and proceed as follows: assuming an empty instruction
pipeline (occurring as a result of a reset, jump, or branch), the
contents of IC are placed on the AD bus as an address. The
returned value, which will be an instruction, is stored in the IA
register.
and the next fetch is performed. This second returned value,
which may be either an instruction or an immediate operand, is
stored in both the IA and Dl registers. The instruction
previously stored in IA is advanced to IB to be executed.
immediate operand is required. If so, that operand has already
been pre-fetched and resides in both IA and Dl. If not, then the
value currently in IA is an instruction. If IA contains an operand,
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Once initialisation has been completed, the module will
Internal CPU cycles are used to perform all CPU data
Instruction Fetches are used to keep the instruction
Instruction fetches are characterised by IN/OPN high but
The value in IC is incremented (via its dedicated counter)
Instruction fetches use instruction pipeline registers IA and
The instruction in IB is checked to determine if an
another instruction fetch is performed and the returned value is
stored only in IA (the contents of IB and Dl are preserved). If IA
contains an instruction, however, the next fetch is deferred
until the contents of IB are no longer needed. At that time, the
deferred fetch is performed, IA is advanced to IB for execution,
and the newly returned value is stored in both IA and Dl.
emptied at which time the whole process is repeated .
3.2.3 OPERAND TRANSFERS
be used by an instruction and to save (write out) any results of
an instruction’s execution. Section 6.0 provides timing
characteristics for operand transfers. Machine cycles
associated with operand transfers are a minimum of five
oscillator periods in duration. The RDYN signal may be used to
insert wait states to accommodate slow memory. Machine
cycle counts in Table 7a of Section 4.0 include operand
transfers.
input register (Dl), and data output register (DO). Before the
operand transfer begins, the processor calculates the effective
operand address and stores this value in A. For write transfers,
the processor loads the operand into the DO register.
are referenced to the AS and DSN bus control signals and are
characterised by IN/OPN low and, by M/ION and CDN high.
The transfer begins by placing the contents of A (the address
register) on the AD bus immediately following the SYNCN
high-to-low transition. The AS strobe then goes high to enable
the system’s transparent address latch. The address is
assured valid on the high-to-low transition of AS. The DDN
signal is high during the address portion of the transfer; its
subsequent action depends on whether the transfer is a read
or write.The RDWN signal indicates the direction of the
transfer. If the operand is a write, the address from A is
replaced by the operand in DO when SYNCN transitions from
low-to-high. Next, the DSN signal goes low and can be used by
the memory system to generate a write enable. Data is
guaranteed valid at the low-to-high transition of DSN. DDN
stays high for the duration of a write transfer. The memory
system must pull RDYN low to conclude the transfer.
placed in a high impedance state at the low-to-high transition
of SYNCN to give the memory system access to the bus. Next,
the DSN signal goes low and can be used by the memory
system to generate an output enable. Shortly after DSN goes
low, DDN also goes low. This should be used by the system to
reverse the direction of the system’s AD bus transceivers. The
memory system must pull RDYN low to conclude the transfer.
Data will be read into the Dl register on the SYNCN high-to-low
transition 3.2.4 Input/Output Transfers
VIO protocols and are characterized by M/ION and IN/OPN
low and CDN high. RD/WN defines the direction of the
transfer. AS and DSN cycle as with operand transfer
operations. The procedure followed depends on whether the
transfer is associated with one of the internally implemented
XIO commands or an externally implemented capability. An
exception is the Read Configuration Word (RCW) command
This sequence repeats until the instruction pipeline is again
Operand transfers are used to obtain (read in) operands to
Operand transfers use the address register (A), the data
Input/Output transfers utilize the MIL-STD-1750A XIO and
If the operand transfer is a read, the AD bus drivers are
All operand transfers between the module and memory