DSP101 Burr-Brown Corporation, DSP101 Datasheet - Page 10

• Manufacturer Part Number: DSP101
• Description: DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
• Manufacturer: Burr-Brown Corporation

FIGURE 4. Output Structure of DSP102.
DATA TRANSFER
The internal A/Ds generate 18 bits of data, transmitting the
data MSB first. When read by a DSP IC programmed to
accept 16 bits of data, the first 16 MSB bits of data from the
DSP101, or each channel of the DSP102, will be shifted into
the processor’s input shift register, and the last two least
significant bits of data from the A/D will be ignored,
although they will still be present on the serial data line.
When the DSP processor is programmed to accept words of
more than 16-bit length (typically 24-bit or 32-bit), the
DSP101 and DSP102 will transmit the full 18-bit conversion
results, after which the information input on the TAG input
(or TAGA and TAGB on the DSP102) will be appended to
the output word. (See Tag Feature below.)
In the Cascade Mode, the DSP102 will first transmit the 16
MSBs from channel A, followed by the full 18 bits from
channel B, although DSP processors programmed to accept
32 bits of data will ignore the final two bits of information
on Channel B. See the DSP102 Cascade Mode section below
for details of the Cascade mode.
DATA SYNCHRONIZATION
A convert command both initiates a conversion and starts
the process for transmitting data from the previous conver-
sion. Convert commands can come at any time, completely
asynchronous to the conversion clock or the bit clock, and
Shift/Load
Shift/Load
NOTE: (1) Signal internal to DSP101/DSP102 which also generates SYNC pulse.
CLKIN
CLKIN
CONV
CONV
TAGA
CASC
TAGB
XCLK
XCLK
(1)
(1)
®
DSP101/102
(LSB)
(LSB)
D
D1
D1
D
18
18
RCK
RCK
Channel A Conversion Results from SAR
Channel B Conversion Results from SAR
E
D
16
16
1
D
2
14
14
12
12
18-bit Register
18-bit Register
10
10
10
the conversion clock may also be independent of the bit
clock. The DSP101 and DSP102 internally synchronize the
output data, Sync pulse, and Tag inputs to the bit clock.
While the convert command, conversion clock and bit clock
can be asynchronous, system performance is usually en-
hanced by synchronizing all of them to a system master
clock, whenever the application permits. This minimizes
changes in digital loads and currents when the critical S/H
transition and A/D bit decisions are occurring. Within the
DSP101 and DSP102 themselves, running asynchronous
convert commands, conversion clocks and bit clocks typi-
cally degrades performance only several dB, as shown in the
various typical performance curves, but the system board
design can easily have more effect.
When a convert command is received, the internal logic
generates an appropriate Sync pulse, synchronized to XCLK,
as shown in Figure 1. The output Sync pulse will be active
High or active Low depending on whether a HIGH or a
LOW, respectively, is input at SSF (pin 12).
The convert command also causes the conversion results
from the previous conversion to be loaded into the output
shift register, synchronous to XCLK. Figure 4 shows the
operation of the internal data shift registers on the DSP102.
The DSP101 is basically similar, but includes only the top of
the figure, showing the SOUTA path.
8
8
6
6
18-bit Shift Register
18-bit Shift Register
18-bit Shift Register
18-bit Shift Register
4
4
2
2
(MSB)
(MSB)
1
1
SOUTA
SOUTB