DSP101 Burr-Brown Corporation, DSP101 Datasheet - Page 16

• Manufacturer Part Number: DSP101
• Description: DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
• Manufacturer: Burr-Brown Corporation

of the MSB capacitor in the CDAC. These pins are nomi-
nally at +100mV after laser-trimming during manufacturing.
They can handle external inputs up to about one diode drop
below ground (–0.6V) before internal clamping circuitry is
triggered.
Figure 8 shows an appropriate circuit for adjusting the
weight of the most significant bit to minimize differential
non-linearity at the critical major-carry transition. To adjust,
provide a small amplitude sine wave to the selected A/D
input pin while converting continually, and adjust for maxi-
mum Signal-to-(Noise + Distortion) ratio, using appropriate
signal analysis software.
GAIN ADJUST
If circuit gain needs to be adjusted in hardware, rather than
in system software, appropriate trimpots should be included
in the analog signal conditioning section in front of the
DSP101 or DSP102. No specific gain adjust circuitry is
included in the parts.
APPLICATIONS
INTERFACING DSP101 TO PARALLEL PORTS
Figure 9 shows a circuit for converting the serial output data
from the DSP101 into 16 bits of parallel data, within the
timing constraints of the serial bit-stream from the DSP101.
In many applications, this circuit can be easily incorporated
into gate arrays or other programmed logic circuits already
used in the system, since the extra gate count is not high.
This circuit adds an additional pipeline delay to the conver-
sion data, so that the parallel data from a conversion at time
FIGURE 11. Analog Input and Analog Output System.
Analog Input
±2.75V
®
DSP PROCESSOR
DSP32C, DSP16
DSP56001
DSP56001
TMS320C25/C30
ADSP2101/2105
DSP101/102
2
VIN
DSP101
CONV
SOUT
SYNC
XCLK
SSF
16
20
15
12
21
SYNC FORMAT
Active High
Active High
Active High
Active High
Active Low
SSF
(2)
CLKR
DATA IN
SYNC
SERIAL I/O WORD
Conversion Rate
Digital Signal
Processor IC
Generator
TTL Bit
16 Bits
24 Bits
16 Bits
16 Bits
16 Bits
Clock
DATA OUT
16
SYNC
XCLK
(t) is valid one conversion cycle plus 17 XCLK clocks later
(at t+1 plus 17 times XCLK). A convert command at time
(t+1) generates a Sync and begins transmitting serial data
from SOUT. The serial data is shifted into the 74HC594
shift registers, and Sync is shifted through the 74HC164
shift registers. The Q1 output of the 74HC74 dual D-type
flip-flops clocks the conversion data into the output register
of the 74HC594s, and triggers a data valid signal on its Q2
output. The user can then read the data at any time before the
next conversion is started, and the Read signal will reset the
data valid output from Q2.
In many systems, galvanic isolation of signals is required.
Using opto-couplers on the serial data lines in Figure 9
allows a fully isolated system to be built using a DSP101 and
only three couplers across the barrier (for serial data, XCLK
and SYNC.)
MULTIPLEXING INPUTS TO THE DSP101
Figure 10 shows a complete circuit for sequentially scanning
eight analog input channels with a single DSP101, and using
the Tag feature on the DSP101 to append the multiplexer
channel address to the serial output conversion results.
The circuit in Figure 10 includes the required digital logic
and timing logic. The 74HC163 counter provides the scan
sequence to the Burr-Brown HI-508A analog multiplexer. In
order to allow the HI-508A enough time to switch to the next
channel and settle before the DSP101 begins a conversion,
a 74HC221 one-shot introduces a 3 s delay for the DSP101
convert command input.
The Burr-Brown OPA627 provides a low impedance source
for the DSP101, buffering it from the output impedance of
SSF
HIGH
HIGH
HIGH
HIGH
LOW
SWL
SSF
(2)
(2)
(3)
SWL
12
13
11
10
15
HIGH
HIGH
HIGH
HIGH
LOW
9
(3)
XCLK
SIN
SYNC
SSF
SWL
CONV
(1) See Burr-Brown
DSP201/DSP202
product data sheet
for full description of
this DAC.
DSP201
VOUT
(1)
21
±3V Analog Output