DSP101 Burr-Brown Corporation, DSP101 Datasheet - Page 11

• Manufacturer Part Number: DSP101
• Description: DSP-Compatible Sampling Single/Dual ANALOG-TO-DIGITAL CONVERTERS
• Manufacturer: Burr-Brown Corporation

During the internal successive approximation conversion
process, the conversion results are shifted into the input shift
registers of the output stage on the DSP102. A new convert
command latches that data into the 18-bit parallel latches
shown. The internal signal that also generates the Sync
pulse, labeled “Shift/Load” in Figure 4, synchronously loads
the conversion data into the output shift register on the rising
edge of XCLK. The conversion results are then clocked out
of the shift register on subsequent rising edges of XCLK.
DATA TRANSFER CLOCK
XCLK is the data transfer clock, or bit clock, for the system,
and is an input for the DSP101 or DSP102. This input is
TTL- and 74HC-level compatible. The serial data and SYNC
outputs are synchronized internally to this clock, with data
valid on the rising edge of XCLK, per the timing shown in
Figure 1. Data input on pin 18 (TAG) on the DSP101, or on
pins 18 and 19 on the DSP102 (TAGA and TAGB), will be
clocked into the output shift register on the rising edge of
XCLK, as discussed in the Tag Feature section.
CONVERSION CLOCK
The analog-to-digital converter sections in the DSP101 and
DSP102 were designed to provide accurate conversions
under worst case conditions of supplies, temperatures, etc.
In order to achieve a full 200kHz sampling capability, they
were designed to use a 33% duty cycle conversion clock
(CLKIN on pin 10) as shown in Figure 1. The clock is LOW
FIGURE 6. DSP101 or DSP102 Power Supply Connections.
+5V Analog
–5V Analog
+5V Digital
NOTES: (1) Pin 1 and pin 26 must be bypassed with 10µF tantalum capacitors, on both the DSP101 and DSP102.
(2) Protection from power supply momentary overrange.
+
10µF
10µF
(1)
10
+
+
(2)
0.01µF
10µF
10
11
12
13
14
1
2
3
4
5
6
7
8
9
V –
V +
DGND
DGND
V
VPOTA
DSP101 or DSP102
A
A
D
11
VPOTB
AGND
long enough for internal analog circuitry to settle suffi-
ciently between bit decisions to insure rated accuracy. Bit
decisions in the A/D are then made on the rising edge of
CLKIN.
FIGURE 5. DSP101 or DSP102 Conversion Clock Circuit.
REF
Crystal is CTS Knight MP122 12.288MHz,
20pF load, series resonant mode.
28
27
26
25
24
23
22
21
20
19
18
17
16
15
13
10µF
OSC1
0.1µF
10pF
+
DSP101 or DSP102
12.288MHz
1M
(1)
SAR Clock
= Analog Ground
= Digital Ground
Control
14
DSP101/102
÷3
CLKIN
CLKOUT
10pF
OSC2
synchronous operation
10
11
DSP102's CLKIN for
To other
®