UPD16434 NEC, UPD16434 Datasheet - Page 19

• Manufacturer Part Number: UPD16434
• Description: 1/8/ 1/16 DUTY LCD CONTROLLER/DRIVER
• Manufacturer: NEC

2.6 LCD Voltage Control Circuit
2.7 LCD Timing Control Circuit
2.8 Row/Column Driver
the AC signal synchronized with the CLOCK and SYNC signal, and supplies the signals to determine the select and
non-select level of the row and column signals and the phase for the row and column drivers.
SFF command, and the number of time divisions specified by the SMM command.
to the data memory row/column driver, and LCD voltage control circuit.
the SYNC mode is specified to the input mode, the SYNC signal supplied from some other chip is input to generate the
timing signals in synchronization with each frame interval.
configuration.
C42 to C49, and a dual mode row driver for R0 to R7 or R8 to R15.
This circuit multiplexes the DC voltage supplied from the LCD drive reference voltage inputs (V
This circuit generates the timing signals from the clock signal, according to the frame frequency specified by the
Table 2–1 indicates these signal levels and the phase.
The timing signals are necessary for automatically reading the display data and driving the LCD, and are supplied
If the SYNC signal is set to the output mode by the SMM command, the SYNC signal is output for each frame. If
The SYNC signal input/output function is used to synchronize the LCD drive timing between chips in multi-chip
The row/column driver consists of the column driver for C0 to C41 signals, row/column driver for R15 to R8 and
The dual mode row driver function is determined by the SMM command.
Note V
Row
Column
LC2
= V
LC3
Select
Non-select
Select
Non-select
Table 2–1. LCD Driver Voltage Signal Levels and Phase
V
V
V
V
LC0
LC4
LC5
LC2
Note
Data Sheet S10299EJ4V0DS00
–
8-time-divisions
V
V
V
V
LC5
LC1
LC0
LC2
+
V
V
V
V
LC0
LC4
LC5
LC3
–
16-time-divisions
V
V
V
V
LC1
LC5
LC1
LC0
LC2
to V
PD16434
+
LC5
) with
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