UPD16434 NEC, UPD16434 Datasheet - Page 36

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UPD16434

Manufacturer Part Number
UPD16434
Description
1/8/ 1/16 DUTY LCD CONTROLLER/DRIVER
Manufacturer
NEC
Datasheet

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(2) Clearing standby mode by RESET signal
36
7.2 Stopping Clock Supply and Retaining Data at Low Voltage in Standby Mode
power consumption can be further reduced by stopping the CLOCK supply to the
CLOCK supply to the
the /BUSY signal is high, after executing the STOP command), set the RESET signal to high, then stop the CLOCK
supply to the
the RESET signal can be used to clear the standby mode.
mode is initiated (this can be checked by determining whether the /BUSY is set to high), then set the RESET signal
to low when clearing the standby mode. While the RESET signal is high, the LCD drive voltage becomes the same
as when it is in the reset operation, and no voltage is applied to the LCD. However, unlike normal reset operation,
the contents of the data memory will not become undefined by the RESET signal. The data which existed before
entering the standby mode is retained, and it can be used after clearing the standby mode. In a system which uses
this method, the current path control by the RESET signal shown in Figure5–5 can be used.
In the standby mode, only the data memory contents can be retained at a reduced voltage level. In this case, the
When using the RESET signal for clearing the standby mode, set the RESET signal to high after the standby
For a system for which only the contents of the data memory need be held when the standby mode is cleared,
PD16434 after the specified time period.
Remark The power fed to the CPU and the
PD16434 in the standby mode, check that the
CPU
Output port
V
Figure 7–1. Controlling LCD Drive Voltage
DD
Data Sheet S10299EJ4V0DS00
V
DD
PD16434 must be from the same source.
PD16434 is in the standby mode (check that
V
V
V
V
V
V
DD
LC1
LC2
LC3
LC4
LC5
(V
LC0
PD16434. When stopping the
)
PD16434
PD16434

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