LM3S600 Bookham Technology, Inc., LM3S600 Datasheet - Page 26

• Manufacturer Part Number: LM3S600
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

Architectural Overview
1.4.5.2
1.4.5.3
1.4.6
1.4.6.1
1.4.6.2
26
The GPIO module features programmable interrupt generation as either edge-triggered or
level-sensitive on all pins, programmable control for GPIO pad configuration, and bit masking in
both read and write operations through address lines.
Three Programmable Timers (see page 157)
Programmable timers can be used to count or time external events that drive the Timer input pins.
The Stellaris
block provides two 16-bit timer/counters that can be configured to operate independently as timers
or event counters, or configured to operate as one 32-bit timer or one 32-bit Real-Time Clock (RTC).
When configured in 32-bit mode, a timer can run as a one-shot timer, periodic timer, or Real-Time
Clock (RTC). When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can
extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event
capture or Pulse Width Modulation (PWM) generation.
Watchdog Timer (see page 193)
A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is
reached. The watchdog timer is used to regain control when a system has failed due to a software
error or to the failure of an external device to respond in the expected way.
The Stellaris
register, interrupt generation logic, and a locking register.
The Watchdog Timer can be configured to generate an interrupt to the controller on its first time-out,
and to generate a reset signal on its second time-out. Once the Watchdog Timer has been configured,
the lock register can be written to prevent the timer configuration from being inadvertently altered.
Memory Peripherals
The LM3S600 controller offers both single-cycle SRAM and single-cycle Flash memory.
SRAM (see page 103)
The LM3S600 static random access memory (SRAM) controller supports 8 KB SRAM. The internal
SRAM of the Stellaris
reduce the number of time-consuming read-modify-write (RMW) operations, ARM has introduced
bit-banding technology in the new Cortex-M3 processor. With a bit-band-enabled processor, certain
regions in the memory map (SRAM and peripheral space) can use address aliases to access
individual bits in a single, atomic operation.
Flash (see page 104)
The LM3S600 Flash controller supports 32 KB of flash memory. The flash is organized as a set of
1-KB blocks that can be individually erased. Erasing a block causes the entire contents of the block
to be reset to all 1s. These blocks are paired into a set of 2-KB blocks that can be individually
protected. The blocks can be marked as read-only or execute-only, providing different levels of code
protection. Read-only blocks cannot be erased or programmed, protecting the contents of those
blocks from being modified. Execute-only blocks cannot be erased or programmed, and can only
be read by the controller instruction fetch mechanism, protecting the contents of those blocks from
being read by either the controller or by a debugger.
®
®
General-Purpose Timer Module (GPTM) contains three GPTM blocks. Each GPTM
Watchdog Timer module consists of a 32-bit down counter, a programmable load
®
devices is located at offset 0x0000.0000 of the device memory map. To
Preliminary
October 01, 2007