LM3S600 Bookham Technology, Inc., LM3S600 Datasheet - Page 29

• Manufacturer Part Number: LM3S600
• Description: Microcontroller
• Manufacturer: Bookham Technology, Inc.

2.1
2.2
2.2.1
October 01, 2007
Block Diagram
Figure 2-1. CPU Block Diagram
Functional Description
Important:
Luminary Micro has implemented the ARM Cortex-M3 core as shown in Figure 2-1 on page 29. As
noted in the ARM® Cortex™-M3 Technical Reference Manual, several Cortex-M3 components are
flexible in their implementation: SW/JTAG-DP, ETM, TPIU, the ROM table, the MPU, and the Nested
Vectored Interrupt Controller (NVIC). Each of these is addressed in the sections that follow.
Serial Wire and JTAG Debug
Luminary Micro has replaced the ARM SW-DP and JTAG-DP with the ARM CoreSight™-compliant
Serial Wire JTAG Debug Port (SWJ-DP) interface. This means Chapter 12, “Debug Port,” of the
ARM® Cortex™-M3 Technical Reference Manual does not apply to Stellaris
The SWJ-DP interface combines the SWD and JTAG debug ports into one module. See the
CoreSight™ Design Kit Technical Reference Manual for details on SWJ-DP.
Serial Wire JTAG
Debug Port
The ARM® Cortex™-M3 Technical Reference Manual describes all the features of an
ARM Cortex-M3 in detail. However, these features differ based on the implementation.
This section describes the Stellaris
Controller
Vectored
Interrupt
Nested
Private Peripheral
Access Port
Adv. High-
Interrupts
Perf. Bus
(internal)
Debug
Sleep
Bus
Preliminary
Breakpoint
Patch and
Instructions
Flash
Protection
CM3 Core
Memory
®
Unit
implementation.
Data
Watchpoint
and Trace
Matrix
Bus
Data
Cortex-M3
ARM
Trace Macrocell
Instrumentation
Adv. Peripheral
LM3S600 Microcontroller
®
Bus
devices.
Interface
Trace
I-code bus
D-code bus
System bus
Port
Unit
Peripheral
(external)
Output
(SWO)
Serial
Trace
Table
Private
ROM
Wire
Port
29
Bus