UPD78323 NEC, UPD78323 Datasheet - Page 49

• Manufacturer Part Number: UPD78323
• Description: 16/8-BIT SINGLE-CHIP MICROCONTROLLER
• Manufacturer: NEC

8. INSTRUCTION SET
(1) Operand representation format and description method
representation format (refer to the assembler specification for details). If two or more factors are included in the description
method column, select one factor. The capital alphabetic letters and +, -, #, $, ! and [ ] symbols are keywords and should
be described as they are.
#, $, ! and [ ] symbols.
Note Do not make work access to bit0 = 1 (odd address).
Remarks
Representation
r
r1
r2
rp
rp1
rp2
sfr
sfrp
post
saddr
saddrp
$addr16
!addr16
addr11
addr5
word
byte
bit
n
This chapter covers instruction operations.
For the operation codes and the number of instruction execution clock cycles, see PD78322 User’s Manual (IEU-1248).
In each instruction operand column, enter the operand using the description method for the instruction operand
In case of immediate data, describe appropriate numeric values or labels. When describing labels, make sure to describe
mem
Format
1. Although rp and rp1 have the same describable register names, they generate different codes.
2. r, r1, rp, rp1 and post can be described with absolute names (R0 to R15, RP0 to RP7) as well as functional
3. Immediate addressing is enabled for all spaces. Relative addressing is only enabled from the first address
names (X, A, C, B, E, D, L, H, AX, BC, DE, HL, VP, UP (refer to Table 2-1 for details of the relationships
between the absolute and functional names).
of the subsequent instruction to the range of –128 to +127.
R0, R1, R2, R3, R4, R5, R6, R7, R8, R9, R10, R11, R12, R13, R14, R15
R0, R1, R2, R3, R4, R5, R6, R7
C, B
RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7
RP0, RP1, RP2, RP3, RP4, RP5, RP6, RP7
DE, HL, VP, UP
Special function register code (see Table 2-2)
Special function register code (16-bit operation enable register; see Table 2-2)
RP0, RP1, RP2, RP3, RP4, RP5/PSW, RP6, RP7
(Two or more instructions can be described. Only PUSH and POP instructions can be
described for RP5 and only PUSHU and POPU instructions can be described for PSW.)
[DE], [HL], [DE+], [HL+], [DE-], [HL-], [VP], [UP]
[DE+A], [HL+A], [DE+B], [HL+B], [VP+DE], [VP+HL]
[DE+byte], [HL+byte], [VP+byte], [UP+byte], [SP+byte] ; Based mode
word[A], word[B], word[DE], word[HL]
FE20H to FF1FH Immediate data or label
FE20H to FF1EH Immediate data (bit0 = 0) or label (for 16-bit operation)
0000H to FDFFH Immediate data or label; relative addressing
0000H to FDFFH Immediate data or label; immediate addressing
(Up to FFFFH describable by MOV instruction)
800H to FFFH Immediate data or label
40H to 7EH Immediate data (bit0 = 0)
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
3-bit immediate data (0 to 7)
Table 8-1. Operand Representation and Description Method
Description Method
Note
or label
; Register indirect mode
; Based indexed mode
; Index mode
PD78323, 78324
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