CY28349 SpectraLinear, CY28349 Datasheet - Page 10

• Manufacturer Part Number: CY28349
• Description: FTG
• Manufacturer: SpectraLinear

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Rev 1.0, November 24, 2006
Data Byte 10
Data Byte 11
Data Byte 12
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
Bit
Bit
Bit
Pin#
Pin#
Pin#
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
CPU_Skew2
CPU_Skew1
CPU_Skew0
Fixed 3V66/PCI
PCI_Skew1
PCI_Skew0
3V66_Skew1
3V66_Skew0
ROCV_FREQ_N7
ROCV_FREQ_N6
ROCV_FREQ_N5
ROCV_FREQ_N4
ROCV_FREQ_N3
ROCV_FREQ_N2
ROCV_FREQ_N1
ROCV_FREQ_N0
ROCV_FREQ_SEL
Name
Name
Name
Fixed 3V66 and PCI output mode
CPU skew control
000 = Normal
001 = –150 ps
010 = –300 ps
011 = –450 ps
100 = +150 ps
101 = +300 ps
110 = +450 ps
111 = +600 ps
0 = Disabled
1 = Enabled
When enabled, 3V66 and PCI output frequency will be fixed
at 64 MHz and 32 MHz respectively.
PCI skew control
00 = Normal
01 = –500 ps
10 = Reserved
11 = +500 ps
3V66 skew control
00 = Normal
01 = –150 ps
10 = +150 ps
11 = +300 ps
If ROCV_FREQ_SEL is set, the values programmed in
ROCV_FREQ_N[7:0] and ROCV_FREQ_M[6:0] will be
used to determine the recovery CPU output frequency
when a Watchdog Timer time-out occurs.
The setting of FS_Override bit determines the frequency
ratio for CPU and other output clocks. When FS_Override
bit is cleared, the same frequency ratio stated in the
Latched FS[4:0] register will be used. When it is set, the
frequency ratio stated in the SEL[4:0] register will be used.
ROCV_FREQ_SEL determines the source of the recover
frequency when a Watchdog Timer time-out occurs. The
clock generator will automatically switch to the recovery
CPU frequency based on the selection on
ROCV_FREQ_SEL.
0 = From latched FS[4:0]
1 = From the settings of ROCV_FREQ_N[7:0] &
ROCV_FREQ_M[6:0]
Pin Description
Pin Description
Pin Description
CY28349
Page 10 of 20
Power On
Power On
Power On
Default
Default
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0