CY28437 SpectraLinear, CY28437 Datasheet - Page 2

• Manufacturer Part Number: CY28437
• Description: Clock Generator
• Manufacturer: SpectraLinear

Rev 1.0, November 20, 2006
Pin Description
1,7
2,6
4
5
8
9
10
11
12
13
14,15
16
17,18,19,20,
22,23,24,25,
31,30,33,32,
35,36
21,28,34
26,27
29
37
38
39
42
44,43,41,40 CPUT/C
45
46
47
48
49
50
51
52
53
54
3,55,56
Pin No.
VDD_PCI
VSS_PCI
FS_E/PCI4
PCI
DF_EN/PCIF0
SRESET_EN/PCIF
1
VTT_PWRGD#/PD
VDD_48
FS_A/USB48_0
VSS_48
DOT96T, DOT96C
FS_B/USB48_1
SRCT/C
VDD_SRC
SRC4_SATAT,
SRC4_SATAC
VSS_SRC
VDDA
VSSA
IREF
VDD_CPU
VSS_CPU
SCLK
SDATA
VDD_REF
XOUT
XIN
VSS_REF
FS_D/REF0
FS_C/REF1
PCI0/SRESET#
DF/PCI
Name
I/O, SE,
I/O, PD,
I/O, PD,
I/O, PU,
I/O, SE,
I/O, SE,
I/O, SE
I/O, SE 3.3V LVTTL input for Dynamic Frequency/33-MHz clocks output.
O, DIF Fixed 96-MHz clock output.
O, DIF Differential serial reference clocks. Outputs have overclocking capability.
O, DIF Differential serial reference clock. Recommended output for SATA.
O, DIF Differential CPU clock outputs.
O, SE 33 MHz clocks.
O, SE 14.318 MHz crystal output.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for PLL.
PWR 3.3V power supply for outputs.
PWR 3.3V power supply for outputs.
GND
I, PD
GND
GND
GND
GND
GND
Type
PU
PD
SE
SE
SE
I/O
PD
PD
PU
O
I
I
I
Ground for outputs.
3.3V-tolerant input for CPU frequency selection/33-MHz clock.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
3.3V LVTTL input to Enable DF pin/33-MHz Output.
1 = Enable, 0 = Disable.
Intel Type-5 output buffer
3.3V LVTTL input to enable Watchdog/33-MHz clocks.
1 = Enable, 0 = Disable
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,
FS_C, FS_D, and FSE inputs. After VTT_PWRGD# (active LOW) assertion, this pin
becomes a real-time input for asserting power-down (active HIGH).
3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
3.3V-tolerant input for CPU frequency selection/fixed 48-MHz clock output.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
Ground for outputs.
Ground for PLL.
A precision resistor is attached to this pin, which is connected to the internal
current reference.
Ground for outputs.
SMBus-compatible SCLOCK.
SMBus-compatible SDATA.
14.318 MHz crystal input.
Ground for outputs.
3.3V-tolerant input for CPU frequency selection/Reference clock.
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
3.3V-tolerant input for CPU frequency selection/Reference clock.
Selects test mode if pulled to V
Refer to DC Electrical Specifications table for V
33 MHz clocks/3.3V LVTTL output for Watchdog reset.
When configured as SRESET# output this output becomes open drain type with a
high (>100k ) internal pull-up resistor.
IHFS_C
Description
when VTT_PWRGD# is asserted LOW.
ILFS_C
,V
IMFS_C
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,V
IHFS_C
CY28437
specifications.
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